[gem5-dev] Change in gem5/gem5[develop]: arch-power: Fix load-store instructions
Boris Shingarov has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40893 )
Change subject: arch-power: Fix load-store instructions
..
arch-power: Fix load-store instructions
Now that 64-bit registers and operands are being used, the
instructions for words must read or write just one word at
a time. This fixes the following instructions.
* Load Word and Zero (lwz)
* Load Word and Zero Indexed (lwzx)
* Load Word and Zero with Update (lwzu)
* Load Word and Zero with Update Indexed (lwzux)
* Load Word And Reserve Indexed (lwarx)
* Store Word (stw)
* Store Word Indexed (stwx)
* Store Word with Update (stwu)
* Store Word with Update Indexed (stwux)
* Store Word Conditional Indexed (stwcx.)
This also fixes decoding of load-store update instructions
for some special scenarios when RA is zero or RA and RT
are the same. In such cases, the instruction is considered
invalid.
Change-Id: I6787d3614ba8f1b1cbf30a49f85ef422324d7c21
Signed-off-by: Sandipan Das
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40893
Reviewed-by: Boris Shingarov
Maintainer: Jason Lowe-Power
Tested-by: kokoro
---
M src/arch/power/isa/decoder.isa
M src/arch/power/isa/formats/mem.isa
M src/arch/power/isa/formats/util.isa
3 files changed, 37 insertions(+), 9 deletions(-)
Approvals:
Boris Shingarov: Looks good to me, approved
Jason Lowe-Power: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index 0cf6201..c81e65b 100644
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -196,8 +196,12 @@
}});
format LoadIndexOp {
-20: lwarx({{ Rt = Mem_sw; Rsv = 1; RsvLen = 4; RsvAddr = EA;
}});
-23: lwzx({{ Rt = Mem; }});
+20: lwarx({{
+Rt = Mem_uw;
+Rsv = 1; RsvLen = 4; RsvAddr = EA;
+}});
+
+23: lwzx({{ Rt = Mem_uw; }});
}
format IntLogicOp {
@@ -219,7 +223,7 @@
CR = insertCRField(CR, BF, cr);
}});
-55: LoadIndexUpdateOp::lwzux({{ Rt = Mem; }});
+55: LoadIndexUpdateOp::lwzux({{ Rt = Mem_uw; }});
60: IntLogicOp::andc({{ Ra = Rs & ~Rb; }});
87: LoadIndexOp::lbzx({{ Rt = Mem_ub; }});
119: LoadIndexUpdateOp::lbzux({{ Rt = Mem_ub; }});
@@ -228,7 +232,7 @@
format StoreIndexOp {
150: stwcx({{
bool store_performed = false;
-Mem = Rs;
+Mem_uw = Rs_uw;
if (Rsv) {
if (RsvLen == 4) {
if (RsvAddr == EA) {
@@ -243,7 +247,7 @@
Rsv = 0;
}});
-151: stwx({{ Mem = Rs; }});
+151: stwx({{ Mem_uw = Rs_uw; }});
}
183: StoreIndexUpdateOp::stwux({{ Mem = Rs; }});
@@ -515,12 +519,12 @@
}
}
-32: LoadDispOp::lwz({{ Rt = Mem; }});
-33: LoadDispUpdateOp::lwzu({{ Rt = Mem; }});
+32: LoadDispOp::lwz({{ Rt = Mem_uw; }});
+33: LoadDispUpdateOp::lwzu({{ Rt = Mem_uw; }});
34: LoadDispOp::lbz({{ Rt = Mem_ub; }});
35: LoadDispUpdateOp::lbzu({{ Rt = Mem_ub; }});
-36: StoreDispOp::stw({{ Mem = Rs; }});
-37: StoreDispUpdateOp::stwu({{ Mem = Rs; }});
+36: StoreDispOp::stw({{ Mem_uw = Rs_uw; }});
+37: StoreDispUpdateOp::stwu({{ Mem_uw = Rs_uw; }});
38: StoreDispOp::stb({{ Mem_ub = Rs_ub; }});
39: StoreDispUpdateOp::stbu({{ Mem_ub = Rs_ub; }});
40: LoadDispOp::lhz({{ Rt = Mem_uh; }});
diff --git a/src/arch/power/isa/formats/mem.isa
b/src/arch/power/isa/formats/mem.isa
index 8e6567d..d2b3ab7 100644
--- a/src/arch/power/isa/formats/mem.isa
+++ b/src/arch/power/isa/formats/mem.isa
@@ -263,6 +263,7 @@
(header_output, decoder_output, decode_block, exec_output) = \
LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags,
inst_flags,
base_class = 'MemIndexOp',
+ decode_template = CheckRaRtDecode,
exec_template_base = 'Load')
}};
@@ -277,6 +278,7 @@
(header_output, decoder_output, decode_block, exec_output) = \
LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags,
inst_flags,
base_class = 'MemIndexOp',
+ decode_template = CheckRaZeroDecode,
exec_template_base = 'Store')
}};
@@ -319,6 +321,7 @@
(header_output, decoder_output, decode_block, exec_output) = \
LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags,
inst_flags,
base_class = 'MemDispOp',
+ decode_template = CheckRaRtDecode,
exec_template_base = 'Load')
}};
@@ -333,5 +336,6 @@
(header_output, decoder_output, decode_block, exec_output) = \
[gem5-dev] Change in gem5/gem5[develop]: arch-power: Fix load-store instructions for timing cpu
Sandipan Das has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/40947 )
Change subject: arch-power: Fix load-store instructions for timing cpu
..
arch-power: Fix load-store instructions for timing cpu
To properly implement load-store instructions for use with
the TimingSimpleCPU model, the initiateAcc() part of the
instruction should only be responsible for performing the
effective address computation and then initiating memory
access.
The completeAcc() part of the instruction should then be
responsible for setting the condition register flags or
updating the base register based on the outcome of the
memory access. This fixes the following instructions:
* Load Byte and Zero with Update (lbzu)
* Load Halfword and Zero with Update (lhzu)
* Load Halfword Algebraic with Update (lhau)
* Load Word and Zero with Update (lwzu)
* Load Doubleword with Update (ldu)
* Load Floating Single with Update (lfsu)
* Load Floating Double with Update (lfdu)
* Load Byte and Zero with Update Indexed (lbzux)
* Load Halfword and Zero with Update Indexed (lhzux)
* Load Halfword Algebraic with Update Indexed (lhaux)
* Load Word and Zero with Update Indexed (lwzux)
* Load Word Algebraic with Update Indexed (lwaux)
* Load Doubleword with Update Indexed (ldux)
* Load Floating Single with Update Indexed (lfsux)
* Load Floating Double with Update Indexed (lfdux)
* Load Byte And Reserve Indexed (lbarx)
* Load Halfword And Reserve Indexed (lharx)
* Load Word And Reserve Indexed (lwarx)
* Load Doubleword And Reserve Indexed (ldarx)
* Store Byte with Update (stbu)
* Store Halfword with Update (sthu)
* Store Word with Update (stwu)
* Store Doubleword with Update (stdu)
* Store Byte with Update Indexed (stbux)
* Store Halfword with Update Indexed (sthux)
* Store Word with Update Indexed (stwux)
* Store Doubleword with Update Indexed (stdux)
* Store Byte Conditional Indexed (stbcx.)
* Store Halfword Conditional Indexed (sthcx.)
* Store Word Conditional Indexed (stwcx.)
* Store Doubleword Conditional Indexed (stdcx.)
* Store Floating Single with Update (stfsu)
* Store Floating Double with Update (stdsu)
* Store Floating Single with Update Indexed (stfsux)
* Store Floating Double with Update Indexed (stfdux)
Change-Id: If5f720619ec3c40a90c1362a9dfc8cc204e57acf
Signed-off-by: Sandipan Das
---
M src/arch/power/isa/decoder.isa
M src/arch/power/isa/formats/mem.isa
M src/arch/power/isa/formats/util.isa
3 files changed, 73 insertions(+), 43 deletions(-)
diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index aeee29a..1db8159 100644
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -313,17 +313,21 @@
// Ra and Rb are source registers, Rt is the destintation.
format LoadIndexOp {
87: lbzx({{ Rt = Mem_ub; }});
-52: lbarx({{ Rt = Mem_ub; Rsv = 1; RsvLen = 1; RsvAddr = EA;
}});
+52: lbarx({{ Rt = Mem_ub; }},
+ {{ Rsv = 1; RsvLen = 1; RsvAddr = EA; }});
279: lhzx({{ Rt = Mem_uh; }});
343: lhax({{ Rt = Mem_sh; }});
-116: lharx({{ Rt = Mem_uh; Rsv = 1; RsvLen = 2; RsvAddr = EA;
}});
+116: lharx({{ Rt = Mem_uh;}},
+ {{ Rsv = 1; RsvLen = 2; RsvAddr = EA; }});
790: lhbrx({{ Rt = swap_byte(Mem_uh); }});
23: lwzx({{ Rt = Mem_uw; }});
341: lwax({{ Rt = Mem_sw; }});
-20: lwarx({{ Rt = Mem_uw; Rsv = 1; RsvLen = 4; RsvAddr = EA;
}});
+20: lwarx({{ Rt = Mem_uw; }},
+ {{ Rsv = 1; RsvLen = 4; RsvAddr = EA; }});
534: lwbrx({{ Rt = swap_byte(Mem_uw); }});
21: ldx({{ Rt = Mem; }});
-84: ldarx({{ Rt = Mem_ud; Rsv = 1; RsvLen = 8; RsvAddr = EA;
}});
+84: ldarx({{ Rt = Mem_ud; }},
+ {{ Rsv = 1; RsvLen = 8; RsvAddr = EA; }});
532: ldbrx({{ Rt = swap_byte(Mem); }});
535: lfsx({{ Ft_sf = Mem_sf; }});
599: lfdx({{ Ft = Mem_df; }});
@@ -344,8 +348,9 @@
format StoreIndexOp {
215: stbx({{ Mem_ub = Rs_ub; }});
694: stbcx({{
-bool store_performed = false;
Mem_ub = Rs_ub;
+}}, {{
+bool store_performed = false;
if (Rsv) {
if (RsvLen == 1) {
if (RsvAddr == EA) {
@@ -361,8 +366,9 @@
}});
407: sthx({{ Mem_uh = Rs_uh; }});
726: sthcx({{
-bool store_performed = false;
Mem_uh = Rs_uh;
+}}, {{
+bool store_performed = false;
if (Rsv) {
if (RsvLen == 2) {
if (RsvAddr == EA) {
@@ -379,8
[gem5-dev] Change in gem5/gem5[develop]: arch-power: Fix load-store instructions
Sandipan Das has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/40893 )
Change subject: arch-power: Fix load-store instructions
..
arch-power: Fix load-store instructions
Now that 64-bit registers and operands are being used, the
instructions for words must read or write just one word at
a time. This fixes the following instructions.
* Load Word and Zero (lwz)
* Load Word and Zero Indexed (lwzx)
* Load Word and Zero with Update (lwzu)
* Load Word and Zero with Update Indexed (lwzux)
* Load Word And Reserve Indexed (lwarx)
* Store Word (stw)
* Store Word Indexed (stwx)
* Store Word with Update (stwu)
* Store Word with Update Indexed (stwux)
* Store Word Conditional Indexed (stwcx.)
This also fixes decoding of load-store update instructions
for some special scenarios when RA is zero or RA and RT
are the same. In such cases, the instruction is considered
invalid.
Change-Id: I6787d3614ba8f1b1cbf30a49f85ef422324d7c21
Signed-off-by: Sandipan Das
---
M src/arch/power/isa/decoder.isa
M src/arch/power/isa/formats/mem.isa
M src/arch/power/isa/formats/util.isa
3 files changed, 34 insertions(+), 10 deletions(-)
diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index b9fc811..e2b3929 100644
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -128,7 +128,7 @@
34: lbz({{ Rt = Mem_ub; }});
40: lhz({{ Rt = Mem_uh; }});
42: lha({{ Rt = Mem_sh; }});
-32: lwz({{ Rt = Mem; }});
+32: lwz({{ Rt = Mem_uw; }});
}
58: decode DS_XO {
@@ -141,19 +141,19 @@
35: lbzu({{ Rt = Mem_ub; }});
41: lhzu({{ Rt = Mem_uh; }});
43: lhau({{ Rt = Mem_sh; }});
-33: lwzu({{ Rt = Mem; }});
+33: lwzu({{ Rt = Mem_uw; }});
}
format StoreDispOp {
38: stb({{ Mem_ub = Rs_ub; }});
44: sth({{ Mem_uh = Rs_uh; }});
-36: stw({{ Mem = Rs; }});
+36: stw({{ Mem_uw = Rs_uw; }});
}
format StoreDispUpdateOp {
39: stbu({{ Mem_ub = Rs_ub; }});
45: sthu({{ Mem_uh = Rs_uh; }});
-37: stwu({{ Mem = Rs; }});
+37: stwu({{ Mem_uw = Rs_uw; }});
}
format IntImmArithCheckRaOp {
@@ -233,9 +233,9 @@
87: lbzx({{ Rt = Mem_ub; }});
279: lhzx({{ Rt = Mem_uh; }});
343: lhax({{ Rt = Mem_sh; }});
-23: lwzx({{ Rt = Mem; }});
+23: lwzx({{ Rt = Mem_uw; }});
341: lwax({{ Rt = Mem_sw; }});
-20: lwarx({{ Rt = Mem_sw; Rsv = 1; RsvLen = 4; RsvAddr = EA;
}});
+20: lwarx({{ Rt = Mem_uw; Rsv = 1; RsvLen = 4; RsvAddr = EA;
}});
535: lfsx({{ Ft_sf = Mem_sf; }});
599: lfdx({{ Ft = Mem_df; }});
855: lfiwax({{ Ft_uw = Mem; }});
@@ -245,7 +245,7 @@
119: lbzux({{ Rt = Mem_ub; }});
311: lhzux({{ Rt = Mem_uh; }});
375: lhaux({{ Rt = Mem_sh; }});
-55: lwzux({{ Rt = Mem; }});
+55: lwzux({{ Rt = Mem_uw; }});
373: lwaux({{ Rt = Mem_sw; }});
567: lfsux({{ Ft_sf = Mem_sf; }});
631: lfdux({{ Ft = Mem_df; }});
@@ -254,10 +254,10 @@
format StoreIndexOp {
215: stbx({{ Mem_ub = Rs_ub; }});
407: sthx({{ Mem_uh = Rs_uh; }});
-151: stwx({{ Mem = Rs; }});
+151: stwx({{ Mem_uw = Rs_uw; }});
150: stwcx({{
bool store_performed = false;
-Mem = Rs;
+Mem_uw = Rs_uw;
if (Rsv) {
if (RsvLen == 4) {
if (RsvAddr == EA) {
@@ -276,7 +276,7 @@
format StoreIndexUpdateOp {
247: stbux({{ Mem_ub = Rs_ub; }});
439: sthux({{ Mem_uh = Rs_uh; }});
-183: stwux({{ Mem = Rs; }});
+183: stwux({{ Mem_uw = Rs_uw; }});
}
format IntOp {
diff --git a/src/arch/power/isa/formats/mem.isa
b/src/arch/power/isa/formats/mem.isa
index 1f62571..1dd9854 100644
--- a/src/arch/power/isa/formats/mem.isa
+++ b/src/arch/power/isa/formats/mem.isa
@@ -263,6 +263,7 @@
(header_output, decoder_output, decode_block, exec_output) = \
LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags,
inst_flags,
base_class = 'MemIndexOp',
+ decode_template = CheckRaRtDecode,
exec_template_base = 'Load')
}};
@@ -277,6 +278,7 @@
(header_output, decoder_output, decode_block, exec_output) = \
LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags,
inst_flags,
base_class = 'MemIndexOp',
+ decode_template = CheckRaZeroDecode,
exec_template_base = 'Store')
}};
@@ -319,6 +321,7 @@
(header_output, decoder_output, decode_block,
