[gem5-dev] Change in gem5/gem5[develop]: arch-power: Refactor load-store instructions

2021-05-07 Thread Boris Shingarov (Gerrit) via gem5-dev 
Boris Shingarov has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/40892 )


Change subject: arch-power: Refactor load-store instructions
..

arch-power: Refactor load-store instructions

This changes the base classes for load-store instructions
and introduces two new classes for DS form instructions
which use a shifted signed immediate field as the offset
from the base address and for X form instructions which
use registers for both the offset and the base address.
The formats have also been updated to make use of the new
base classes.

Change-Id: Ib5d1bb5d7747813e0e5b1e3075489f1a3aa72660
Signed-off-by: Sandipan Das 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40892
Reviewed-by: Boris Shingarov 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/arch/power/insts/mem.cc
M src/arch/power/insts/mem.hh
M src/arch/power/isa/decoder.isa
M src/arch/power/isa/formats/mem.isa
4 files changed, 57 insertions(+), 16 deletions(-)

Approvals:
  Boris Shingarov: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/power/insts/mem.cc b/src/arch/power/insts/mem.cc
index 596d78d..4c2688c 100644
--- a/src/arch/power/insts/mem.cc
+++ b/src/arch/power/insts/mem.cc
@@ -63,7 +63,7 @@
 }

 // Print the displacement
-ss << ", " << (int32_t)disp;
+ss << ", " << d;

 // Print the address register
 ss << "(";
diff --git a/src/arch/power/insts/mem.hh b/src/arch/power/insts/mem.hh
index de9b46c..e982515 100644
--- a/src/arch/power/insts/mem.hh
+++ b/src/arch/power/insts/mem.hh
@@ -63,11 +63,12 @@
 {
   protected:

-int16_t disp;
+int64_t d;

 /// Constructor
 MemDispOp(const char *mnem, MachInst _machInst, OpClass __opClass)
-  : MemOp(mnem, _machInst, __opClass), disp(machInst.d)
+  : MemOp(mnem, _machInst, __opClass),
+d(sext<16>(machInst.d))
 {
 }

@@ -75,6 +76,38 @@
 Addr pc, const Loader::SymbolTable *symtab) const override;
 };

+/**
+ * Class for memory operations with shifted displacement.
+ */
+class MemDispShiftOp : public MemOp
+{
+  protected:
+
+int64_t ds;
+
+/// Constructor
+MemDispShiftOp(const char *mnem, MachInst _machInst, OpClass __opClass)
+  : MemOp(mnem, _machInst, __opClass),
+ds(sext<14>(machInst.ds))
+{
+}
+};
+
+
+/**
+ * Class for memory operations with register indexed addressing.
+ */
+class MemIndexOp : public MemOp
+{
+  protected:
+
+/// Constructor
+MemIndexOp(const char *mnem, MachInst _machInst, OpClass __opClass)
+  : MemOp(mnem, _machInst, __opClass)
+{
+}
+};
+
 } // namespace PowerISA

 #endif //__ARCH_POWER_INSTS_MEM_HH__
diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index ac52ab3..e00ce3b 100644
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -527,9 +527,7 @@
 55: StoreDispUpdateOp::stfdu({{ Mem_df = Fs; }});

 58: decode DS_XO {
-2: LoadDispOp::lwa({{ Rt = Mem_sw; }},
-   {{ EA = Ra + (disp & 0xfffc); }},
-   {{ EA = disp & 0xfffc; }});
+2: LoadDispShiftOp::lwa({{ Rt = Mem_sw; }});
 }

 format FloatArithOp {
diff --git a/src/arch/power/isa/formats/mem.isa  
b/src/arch/power/isa/formats/mem.isa

index c7be2b1..1b2500c 100644
--- a/src/arch/power/isa/formats/mem.isa
+++ b/src/arch/power/isa/formats/mem.isa
@@ -240,7 +240,7 @@
mem_flags = [], inst_flags = []) {{
 (header_output, decoder_output, decode_block, exec_output) = \
 GenMemOp(name, Name, memacc_code, ea_code, ea_code_ra0,
- 'MemOp', 'Load', mem_flags, inst_flags)
+ 'MemIndexOp', 'Load', mem_flags, inst_flags)
 }};


@@ -249,7 +249,7 @@
 mem_flags = [], inst_flags = []) {{
 (header_output, decoder_output, decode_block, exec_output) = \
 GenMemOp(name, Name, memacc_code, ea_code, ea_code_ra0,
- 'MemOp', 'Store', mem_flags, inst_flags)
+ 'MemIndexOp', 'Store', mem_flags, inst_flags)
 }};


@@ -262,7 +262,7 @@
 # Generate the class
 (header_output, decoder_output, decode_block, exec_output) = \
 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags,  
inst_flags,

-  base_class = 'MemOp',
+  base_class = 'MemIndexOp',
   exec_template_base = 'Load')
 }};

@@ -276,13 +276,13 @@
 # Generate the class
 (header_output, decoder_output, decode_block, exec_output) = \
 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags,  
inst_flags,

-  base_class = 'MemOp',
+  base_class = 'MemIndexOp',
   exec_template_base = 'Store')
 }};


-def format LoadDispOp(memacc_code, ea_code = {{ EA = Ra + disp;

[gem5-dev] Change in gem5/gem5[develop]: arch-power: Refactor load-store instructions

2021-02-07 Thread Sandipan Das (Gerrit) via gem5-dev 
Sandipan Das has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/40892 )



Change subject: arch-power: Refactor load-store instructions
..

arch-power: Refactor load-store instructions

This changes the base classes for load-store instructions
and introduces two new classes for DS form instructions
which use a shifted signed immediate field as the offset
from the base address and for X form instructions which
use registers for both the offset and the base address.
The formats have also been updated to make use of the new
base classes.

Change-Id: Ib5d1bb5d7747813e0e5b1e3075489f1a3aa72660
Signed-off-by: Sandipan Das 
---
M src/arch/power/insts/mem.hh
M src/arch/power/isa/decoder.isa
M src/arch/power/isa/formats/mem.isa
3 files changed, 48 insertions(+), 8 deletions(-)



diff --git a/src/arch/power/insts/mem.hh b/src/arch/power/insts/mem.hh
index de9b46c..d14f1e6 100644
--- a/src/arch/power/insts/mem.hh
+++ b/src/arch/power/insts/mem.hh
@@ -75,6 +75,38 @@
 Addr pc, const Loader::SymbolTable *symtab) const override;
 };

+/**
+ * Class for memory operations with shifted displacement.
+ */
+class MemDispShiftOp : public MemOp
+{
+  protected:
+
+int16_t disp;
+
+/// Constructor
+MemDispShiftOp(const char *mnem, MachInst _machInst, OpClass __opClass)
+  : MemOp(mnem, _machInst, __opClass),
+disp(sext<14>(machInst.ds))
+{
+}
+};
+
+
+/**
+ * Class for memory operations with register indexed addressing.
+ */
+class MemIndexOp : public MemOp
+{
+  protected:
+
+/// Constructor
+MemIndexOp(const char *mnem, MachInst _machInst, OpClass __opClass)
+  : MemOp(mnem, _machInst, __opClass)
+{
+}
+};
+
 } // namespace PowerISA

 #endif //__ARCH_POWER_INSTS_MEM_HH__
diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index 4005da8..b9fc811 100644
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -132,10 +132,8 @@
 }

 58: decode DS_XO {
-format LoadDispOp {
-2: lwa({{ Rt = Mem_sw; }},
-   {{ EA = Ra + (disp & 0xfffc); }},
-   {{ EA = disp & 0xfffc; }});
+format LoadDispShiftOp {
+2: lwa({{ Rt = Mem_sw; }});
 }
 }

diff --git a/src/arch/power/isa/formats/mem.isa  
b/src/arch/power/isa/formats/mem.isa

index c7be2b1..1f62571 100644
--- a/src/arch/power/isa/formats/mem.isa
+++ b/src/arch/power/isa/formats/mem.isa
@@ -240,7 +240,7 @@
mem_flags = [], inst_flags = []) {{
 (header_output, decoder_output, decode_block, exec_output) = \
 GenMemOp(name, Name, memacc_code, ea_code, ea_code_ra0,
- 'MemOp', 'Load', mem_flags, inst_flags)
+ 'MemIndexOp', 'Load', mem_flags, inst_flags)
 }};


@@ -249,7 +249,7 @@
 mem_flags = [], inst_flags = []) {{
 (header_output, decoder_output, decode_block, exec_output) = \
 GenMemOp(name, Name, memacc_code, ea_code, ea_code_ra0,
- 'MemOp', 'Store', mem_flags, inst_flags)
+ 'MemIndexOp', 'Store', mem_flags, inst_flags)
 }};


@@ -262,7 +262,7 @@
 # Generate the class
 (header_output, decoder_output, decode_block, exec_output) = \
 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags,  
inst_flags,

-  base_class = 'MemOp',
+  base_class = 'MemIndexOp',
   exec_template_base = 'Load')
 }};

@@ -276,7 +276,7 @@
 # Generate the class
 (header_output, decoder_output, decode_block, exec_output) = \
 LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags,  
inst_flags,

-  base_class = 'MemOp',
+  base_class = 'MemIndexOp',
   exec_template_base = 'Store')
 }};

@@ -299,6 +299,16 @@
 }};


+def format LoadDispShiftOp(memacc_code,
+   ea_code = {{ EA = Ra + (disp << 2); }},
+   ea_code_ra0 = {{ EA = (disp << 2); }},
+   mem_flags = [], inst_flags = []) {{
+(header_output, decoder_output, decode_block, exec_output) = \
+GenMemOp(name, Name, memacc_code, ea_code, ea_code_ra0,
+ 'MemDispShiftOp', 'Load', mem_flags, inst_flags)
+}};
+
+
 def format LoadDispUpdateOp(memacc_code, ea_code = {{ EA = Ra + disp; }},
 mem_flags = [], inst_flags = []) {{


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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ib5d1bb5d7747813e0e5b1e3075489f1a3aa72660
Gerrit-Change-Number: 40892
Gerrit-PatchSet: 1
Gerrit-Owner: Sandipan Das 
Gerrit-MessageType: newchange