Yu-hsin Wang has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/48867 )
Change subject: fastmodel: add memory space id map and getter
..
fastmodel: add memory space id map and getter
Change-Id: Ia9bd467b72ed59ba2b3d2aaf402761779c4e76e9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/48867
Reviewed-by: Gabe Black
Maintainer: Gabe Black
Tested-by: kokoro
---
M src/arch/arm/fastmodel/iris/thread_context.cc
M src/arch/arm/fastmodel/iris/thread_context.hh
2 files changed, 19 insertions(+), 0 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/fastmodel/iris/thread_context.cc
b/src/arch/arm/fastmodel/iris/thread_context.cc
index 87e4e77..0d2f0b3 100644
--- a/src/arch/arm/fastmodel/iris/thread_context.cc
+++ b/src/arch/arm/fastmodel/iris/thread_context.cc
@@ -45,6 +45,7 @@
#include
#include "arch/arm/fastmodel/iris/cpu.hh"
+#include "arch/arm/fastmodel/iris/memory_spaces.hh"
#include "arch/arm/system.hh"
#include "arch/arm/utility.hh"
#include "base/logging.hh"
@@ -70,6 +71,10 @@
suspend();
call().memory_getMemorySpaces(_instId, memorySpaces);
+for (const auto : memorySpaces) {
+memorySpaceIds.emplace(
+Iris::CanonicalMsn(space.canonicalMsn), space.spaceId);
+}
call().memory_getUsefulAddressTranslations(_instId, translations);
typedef ThreadContext Self;
@@ -120,6 +125,13 @@
}
}
+iris::MemorySpaceId
+ThreadContext::getMemorySpaceId(const Iris::CanonicalMsn& msn) const
+{
+auto it = memorySpaceIds.find(msn);
+return it == memorySpaceIds.end() ? iris::IRIS_UINT64_MAX : it->second;
+}
+
void
ThreadContext::maintainStepping()
{
diff --git a/src/arch/arm/fastmodel/iris/thread_context.hh
b/src/arch/arm/fastmodel/iris/thread_context.hh
index d16b480..ddc08eb1 100644
--- a/src/arch/arm/fastmodel/iris/thread_context.hh
+++ b/src/arch/arm/fastmodel/iris/thread_context.hh
@@ -31,7 +31,9 @@
#include
#include
#include
+#include
+#include "arch/arm/fastmodel/iris/memory_spaces.hh"
#include "arch/arm/regs/vec.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
@@ -56,6 +58,9 @@
typedef std::vector ResourceIds;
typedef std::map IdxNameMap;
+typedef std::unordered_map
+MemorySpaceMap;
+
protected:
gem5::BaseCPU *_cpu;
int _threadId;
@@ -81,6 +86,7 @@
const ResourceMap , const std::string );
void extractResourceMap(ResourceIds ,
const ResourceMap , const IdxNameMap _names);
+iris::MemorySpaceId getMemorySpaceId(const Iris::CanonicalMsn& msn)
const;
ResourceIds miscRegIds;
@@ -97,6 +103,7 @@
std::vector memorySpaces;
std::vector
translations;
+MemorySpaceMap memorySpaceIds;
// A queue to keep track of instruction count based events.
EventQueue comInstEventQueue;
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ia9bd467b72ed59ba2b3d2aaf402761779c4e76e9
Gerrit-Change-Number: 48867
Gerrit-PatchSet: 2
Gerrit-Owner: Yu-hsin Wang
Gerrit-Reviewer: Earl Ou
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Gabe Black
Gerrit-Reviewer: Yu-hsin Wang
Gerrit-Reviewer: kokoro
Gerrit-MessageType: merged
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