[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: MESI_Three_level prefetcher page crossing

2020-05-02 Thread Pouya Fotouhi (Gerrit) via gem5-dev
Pouya Fotouhi has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/28048 )


Change subject: mem-ruby: MESI_Three_level prefetcher page crossing
..

mem-ruby: MESI_Three_level prefetcher page crossing

This patch allows MESI_Three_level using the Ruby prefetcher to
safely cross page boundaries by determining if an address is bad
and cannot be mapped to a memory controller.

Change-Id: I675a13dfa6deb5b6a9f986ced5a3130436db911d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28048
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
Tested-by: kokoro 
---
M configs/ruby/MESI_Three_Level.py
M src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
2 files changed, 16 insertions(+), 2 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/configs/ruby/MESI_Three_Level.py  
b/configs/ruby/MESI_Three_Level.py

index 0e9ef09..61d6c52 100644
--- a/configs/ruby/MESI_Three_Level.py
+++ b/configs/ruby/MESI_Three_Level.py
@@ -127,7 +127,7 @@
 nonunit_filter = 256,
 train_misses = 5,
 num_startup_pfs = 4,
-cross_page = False
+cross_page = True
 )

 l0_cntrl = L0Cache_Controller(
diff --git a/src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm  
b/src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm

index da89bf5..3639ef2 100644
--- a/src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
+++ b/src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
@@ -140,6 +140,7 @@
 PF_Load, desc="Load request from prefetcher";
 PF_Ifetch,   desc="Instruction fetch request from prefetcher";
 PF_Store,desc="Exclusive load request from prefetcher";
+PF_Bad_Addr, desc="Throw away prefetch request due to bad address  
generation";

   }

   // TYPES
@@ -323,7 +324,16 @@
   in_port(optionalQueue_in, RubyRequest, prefetchQueue, desc="...", rank =  
2) {

 if (optionalQueue_in.isReady(clockEdge())) {
   peek(optionalQueue_in, RubyRequest) {
-if (in_msg.Type == RubyRequestType:IFETCH) {
+// first check for valid address
+MachineID mid := mapAddressToMachine(in_msg.LineAddress,  
MachineType:Directory);

+NodeID nid := machineIDToNodeID(mid);
+int nidint := IDToInt(nid);
+int numDirs := machineCount(MachineType:Directory);
+if (nidint >= numDirs) {
+  Entry cache_entry := static_cast(Entry, "pointer",  
Dcache.getNullEntry());

+  TBE tbe := TBEs.getNullEntry();
+  trigger(Event:PF_Bad_Addr, in_msg.LineAddress, cache_entry, tbe);
+} else if (in_msg.Type == RubyRequestType:IFETCH) {
   // Instruction Prefetch
   Entry icache_entry := getICacheEntry(in_msg.LineAddress);
   if (is_valid(icache_entry)) {
@@ -1164,4 +1174,8 @@
 o_popIncomingResponseQueue;
 kd_wakeUpDependents;
   }
+
+  transition(I, PF_Bad_Addr) {
+pq_popPrefetchQueue;
+  }
 }

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/28048
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I675a13dfa6deb5b6a9f986ced5a3130436db911d
Gerrit-Change-Number: 28048
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Ciro Santilli 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Pouya Fotouhi 
Gerrit-Reviewer: Timothy Hayes 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: MESI_Three_level prefetcher page crossing

2020-04-22 Thread Giacomo Travaglini (Gerrit) via gem5-dev

Hello Timothy Hayes,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/28048

to review the following change.


Change subject: mem-ruby: MESI_Three_level prefetcher page crossing
..

mem-ruby: MESI_Three_level prefetcher page crossing

This patch allows MESI_Three_level using the Ruby prefetcher to
safely cross page boundaries by determining if an address is bad
and cannot be mapped to a memory controller.

Change-Id: I675a13dfa6deb5b6a9f986ced5a3130436db911d
---
M configs/ruby/MESI_Three_Level.py
M src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
2 files changed, 16 insertions(+), 2 deletions(-)



diff --git a/configs/ruby/MESI_Three_Level.py  
b/configs/ruby/MESI_Three_Level.py

index 429fd25..5a69ba8 100644
--- a/configs/ruby/MESI_Three_Level.py
+++ b/configs/ruby/MESI_Three_Level.py
@@ -127,7 +127,7 @@
 nonunit_filter = 256,
 train_misses = 5,
 num_startup_pfs = 4,
-cross_page = False
+cross_page = True
 )

 l0_cntrl = L0Cache_Controller(
diff --git a/src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm  
b/src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm

index 7c7eca1..a62ed84 100644
--- a/src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
+++ b/src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
@@ -140,6 +140,7 @@
 PF_Load, desc="Load request from prefetcher";
 PF_Ifetch,   desc="Instruction fetch request from prefetcher";
 PF_Store,desc="Exclusive load request from prefetcher";
+PF_Bad_Addr, desc="Throw away prefetch request due to bad address  
generation";

   }

   // TYPES
@@ -323,7 +324,16 @@
   in_port(optionalQueue_in, RubyRequest, prefetchQueue, desc="...", rank =  
2) {

 if (optionalQueue_in.isReady(clockEdge())) {
   peek(optionalQueue_in, RubyRequest) {
-if (in_msg.Type == RubyRequestType:IFETCH) {
+// first check for valid address
+MachineID mid := mapAddressToMachine(in_msg.LineAddress,  
MachineType:Directory);

+NodeID nid := machineIDToNodeID(mid);
+int nidint := IDToInt(nid);
+int numDirs := machineCount(MachineType:Directory);
+if (nidint >= numDirs) {
+  Entry cache_entry := static_cast(Entry, "pointer",  
Dcache.getNullEntry());

+  TBE tbe := TBEs.getNullEntry();
+  trigger(Event:PF_Bad_Addr, in_msg.LineAddress, cache_entry, tbe);
+} else if (in_msg.Type == RubyRequestType:IFETCH) {
   // Instruction Prefetch
   Entry icache_entry := getICacheEntry(in_msg.LineAddress);
   if (is_valid(icache_entry)) {
@@ -1162,4 +1172,8 @@
 o_popIncomingResponseQueue;
 kd_wakeUpDependents;
   }
+
+  transition(I, PF_Bad_Addr) {
+pq_popPrefetchQueue;
+  }
 }

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/28048
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I675a13dfa6deb5b6a9f986ced5a3130436db911d
Gerrit-Change-Number: 28048
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Timothy Hayes 
Gerrit-MessageType: newchange
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