[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: MESI_Three_level prefetcher support
Pouya Fotouhi has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/27715 )
Change subject: mem-ruby: MESI_Three_level prefetcher support
..
mem-ruby: MESI_Three_level prefetcher support
Add support for the Ruby stride prefetcher to MESI_Three_Level.
Change-Id: Id68935e2a7d3ccd0e22a59f43a15f167410632a2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27715
Reviewed-by: Bradford Beckmann
Maintainer: Bradford Beckmann
Tested-by: kokoro
---
M configs/ruby/MESI_Three_Level.py
M src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
M src/mem/ruby/protocol/MESI_Three_Level-L1cache.sm
M src/mem/ruby/protocol/MESI_Three_Level-msg.sm
M src/mem/ruby/protocol/MESI_Two_Level-L2cache.sm
M src/mem/ruby/protocol/RubySlicc_Types.sm
M src/mem/ruby/structures/CacheMemory.hh
M src/mem/ruby/structures/TBETable.hh
8 files changed, 386 insertions(+), 3 deletions(-)
Approvals:
Bradford Beckmann: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/configs/ruby/MESI_Three_Level.py
b/configs/ruby/MESI_Three_Level.py
index fdebea4..0e9ef09 100644
--- a/configs/ruby/MESI_Three_Level.py
+++ b/configs/ruby/MESI_Three_Level.py
@@ -53,6 +53,8 @@
parser.add_option("--l0_transitions_per_cycle", type="int", default=32)
parser.add_option("--l1_transitions_per_cycle", type="int", default=32)
parser.add_option("--l2_transitions_per_cycle", type="int", default=4)
+parser.add_option("--enable-prefetch", action="store_true",
default=False,\
+help="Enable Ruby hardware prefetcher")
return
def create_system(options, full_system, system, dma_ports, bootmem,
@@ -118,10 +120,22 @@
else:
clk_domain = system.cpu[i].clk_domain
+# Ruby prefetcher
+prefetcher = RubyPrefetcher.Prefetcher(
+num_streams=16,
+unit_filter = 256,
+nonunit_filter = 256,
+train_misses = 5,
+num_startup_pfs = 4,
+cross_page = False
+)
+
l0_cntrl = L0Cache_Controller(
version = i * num_cpus_per_cluster + j,
Icache = l0i_cache, Dcache = l0d_cache,
transitions_per_cycle =
options.l0_transitions_per_cycle,
+ prefetcher = prefetcher,
+ enable_prefetch = options.enable_prefetch,
send_evictions = send_evicts(options),
clk_domain = clk_domain,
ruby_system = ruby_system)
@@ -159,6 +173,7 @@
l1_cntrl_nodes.append(l1_cntrl)
# Connect the L0 and L1 controllers
+l0_cntrl.prefetchQueue = MessageBuffer()
l0_cntrl.mandatoryQueue = MessageBuffer()
l0_cntrl.bufferToL1 = MessageBuffer(ordered = True)
l1_cntrl.bufferFromL0 = l0_cntrl.bufferToL1
diff --git a/src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
b/src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
index 14fb07a..da89bf5 100644
--- a/src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
+++ b/src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
@@ -46,6 +46,9 @@
Cycles response_latency := 2;
bool send_evictions;
+ Prefetcher * prefetcher;
+ bool enable_prefetch := "False";
+
// From this node's L0 cache to the network
MessageBuffer * bufferToL1, network="To";
@@ -54,6 +57,9 @@
// Message queue between this controller and the processor
MessageBuffer * mandatoryQueue;
+
+ // Request Buffer for prefetches
+ MessageBuffer * prefetchQueue;
{
// STATES
state_declaration(State, desc="Cache states", default="L0Cache_State_I")
{
@@ -92,6 +98,11 @@
// processor needs to write to it. So, the controller has requested for
// write permission.
SM, AccessPermission:Read_Only, desc="Issued GETX, have not seen
response yet";
+
+// Transient states in which block is being prefetched
+PF_Inst_IS, AccessPermission:Busy, desc="Issued GETS, have not seen
response yet";
+PF_IS, AccessPermission:Busy, desc="Issued GETS, have not seen
response yet";
+PF_IE, AccessPermission:Busy, desc="Issued GETX, have not seen
response yet";
}
// EVENTS
@@ -123,6 +134,12 @@
WB_Ack,desc="Ack for replacement";
Failed_SC,desc="Store conditional request that will fail";
+
+// Prefetch events (generated by prefetcher)
+PF_L0_Replacement, desc="L0 Replacement caused by pretcher",
format="!pr";
+PF_Load, desc="Load request from prefetcher";
+PF_Ifetch, desc="Instruction fetch request from prefetcher";
+PF_Store,desc="Exclusive load request from prefetcher";
}
// TYPES
@@ -132,6 +149,7 @@
State CacheState,desc="cache state";
DataBlock DataBlk, desc="data for the block";
[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: MESI_Three_level prefetcher support
Hello Timothy Hayes,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/27715
to review the following change.
Change subject: mem-ruby: MESI_Three_level prefetcher support
..
mem-ruby: MESI_Three_level prefetcher support
Add support for the Ruby stride prefetcher to MESI_Three_Level. This patch
also allows safely crossing page boundaries by determining an address is
bad and cannot be mapped to a memory controller.
Change-Id: Id68935e2a7d3ccd0e22a59f43a15f167410632a2
---
M configs/ruby/MESI_Three_Level.py
M src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
M src/mem/ruby/protocol/MESI_Three_Level-L1cache.sm
M src/mem/ruby/protocol/MESI_Three_Level-msg.sm
M src/mem/ruby/protocol/MESI_Two_Level-L2cache.sm
M src/mem/ruby/protocol/RubySlicc_Types.sm
M src/mem/ruby/structures/CacheMemory.hh
M src/mem/ruby/structures/TBETable.hh
8 files changed, 408 insertions(+), 3 deletions(-)
diff --git a/configs/ruby/MESI_Three_Level.py
b/configs/ruby/MESI_Three_Level.py
index c05dca3..c6ca85f 100644
--- a/configs/ruby/MESI_Three_Level.py
+++ b/configs/ruby/MESI_Three_Level.py
@@ -53,6 +53,8 @@
parser.add_option("--l0_transitions_per_cycle", type="int", default=32)
parser.add_option("--l1_transitions_per_cycle", type="int", default=32)
parser.add_option("--l2_transitions_per_cycle", type="int", default=4)
+parser.add_option("--disable-prefetch", action="store_true",\
+ help="Disable Ruby hardware prefetcher")
return
def create_system(options, full_system, system, dma_ports, bootmem,
@@ -118,10 +120,22 @@
else:
clk_domain = system.cpu[i].clk_domain
+# Ruby prefetcher
+prefetcher = RubyPrefetcher.Prefetcher(
+num_streams=16,
+unit_filter = 256,
+nonunit_filter = 256,
+train_misses = 5,
+num_startup_pfs = 4,
+cross_page = True
+)
+
l0_cntrl = L0Cache_Controller(
version = i * num_cpus_per_cluster + j,
Icache = l0i_cache, Dcache = l0d_cache,
transitions_per_cycle =
options.l0_transitions_per_cycle,
+ prefetcher = prefetcher,
+ enable_prefetch = not options.disable_prefetch,
send_evictions = send_evicts(options),
clk_domain = clk_domain,
ruby_system = ruby_system)
@@ -159,6 +173,7 @@
l1_cntrl_nodes.append(l1_cntrl)
# Connect the L0 and L1 controllers
+l0_cntrl.prefetchQueue = MessageBuffer()
l0_cntrl.mandatoryQueue = MessageBuffer()
l0_cntrl.bufferToL1 = MessageBuffer(ordered = True)
l1_cntrl.bufferFromL0 = l0_cntrl.bufferToL1
diff --git a/src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
b/src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
index 9844fec..12fa578 100644
--- a/src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
+++ b/src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
@@ -46,6 +46,9 @@
Cycles response_latency := 2;
bool send_evictions;
+ Prefetcher * prefetcher;
+ bool enable_prefetch := "True";
+
// From this node's L0 cache to the network
MessageBuffer * bufferToL1, network="To";
@@ -54,6 +57,9 @@
// Message queue between this controller and the processor
MessageBuffer * mandatoryQueue;
+
+ // Request Buffer for prefetches
+ MessageBuffer * prefetchQueue;
{
// STATES
state_declaration(State, desc="Cache states", default="L0Cache_State_I")
{
@@ -92,6 +98,11 @@
// processor needs to write to it. So, the controller has requested for
// write permission.
SM, AccessPermission:Read_Only, desc="Issued GETX, have not seen
response yet";
+
+// Transient states in which block is being prefetched
+PF_Inst_IS, AccessPermission:Busy, desc="Issued GETS, have not seen
response yet";
+PF_IS, AccessPermission:Busy, desc="Issued GETS, have not seen
response yet";
+PF_IE, AccessPermission:Busy, desc="Issued GETX, have not seen
response yet";
}
// EVENTS
@@ -123,6 +134,13 @@
WB_Ack,desc="Ack for replacement";
Failed_SC,desc="Store conditional request that will fail";
+
+// Prefetch events (generated by prefetcher)
+PF_L0_Replacement, desc="L0 Replacement caused by pretcher",
format="!pr";
+PF_Load, desc="Load request from prefetcher";
+PF_Ifetch, desc="Instruction fetch request from prefetcher";
+PF_Store,desc="Exclusive load request from prefetcher";
+PF_Bad_Addr, desc="Throw away prefetch request due to bad address
generation";
}
// TYPES
@@ -132,6 +150,7 @@
State CacheState,desc="cache state";
DataBlock DataBlk, desc="data for the block";
