[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: fix MESI_Three_Level erroneous transition

2020-05-01 Thread Pouya Fotouhi (Gerrit) via gem5-dev 
Pouya Fotouhi has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/28047 )


Change subject: mem-ruby: fix MESI_Three_Level erroneous transition
..

mem-ruby: fix MESI_Three_Level erroneous transition

The MESI_Three_Level protocol includes a transition in its L1
definition to invalidate an SM state but this transition does
not notify the L0 cache. The unintended side effect of this
allows stale values to be read by the L0 cache. This can cause
incorrect behaviour when executing LL/SC based mutexes. This
patch ensures that all invalidates to SM states are exposed to
the L0 cache.

Change-Id: I7fefabdaa8027fdfa4c9c362abd7e467493196aa
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28047
Reviewed-by: John Alsop 
Reviewed-by: Pouya Fotouhi 
Maintainer: Bobby R. Bruce 
Tested-by: kokoro 
---
M src/mem/ruby/protocol/MESI_Three_Level-L1cache.sm
1 file changed, 3 insertions(+), 2 deletions(-)

Approvals:
  Pouya Fotouhi: Looks good to me, approved
  John Alsop: Looks good to me, but someone else must approve
  Bobby R. Bruce: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/mem/ruby/protocol/MESI_Three_Level-L1cache.sm  
b/src/mem/ruby/protocol/MESI_Three_Level-L1cache.sm

index 00d897a..1890bcc 100644
--- a/src/mem/ruby/protocol/MESI_Three_Level-L1cache.sm
+++ b/src/mem/ruby/protocol/MESI_Three_Level-L1cache.sm
@@ -262,7 +262,8 @@
   }

   bool inL0Cache(State state) {
-if (state == State:S || state == State:E || state == State:M ||
+if (state == State:S || state == State:E ||
+state == State:M || state == State:SM ||
 state == State:S_IL0 || state == State:E_IL0 ||
 state == State:M_IL0 || state == State:SM_IL0) {
 return true;
@@ -996,7 +997,7 @@
   }

   // Transitions from IM
-  transition({IM,SM}, Inv, IM) {
+  transition(IM, Inv, IM) {
 fi_sendInvAck;
 l_popL2RequestQueue;
   }

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I7fefabdaa8027fdfa4c9c362abd7e467493196aa
Gerrit-Change-Number: 28047
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: John Alsop 
Gerrit-Reviewer: Marjan Fariborz 
Gerrit-Reviewer: Nikos Nikoleris 
Gerrit-Reviewer: Pouya Fotouhi 
Gerrit-Reviewer: Timothy Hayes 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: fix MESI_Three_Level erroneous transition

2020-04-22 Thread Giacomo Travaglini (Gerrit) via gem5-dev 

Hello Timothy Hayes,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/c/public/gem5/+/28047

to review the following change.


Change subject: mem-ruby: fix MESI_Three_Level erroneous transition
..

mem-ruby: fix MESI_Three_Level erroneous transition

The MESI_Three_Level protocol includes a transition in its L1
definition to invalidate an SM state but this transition does
not notify the L0 cache. The unintended side effect of this
allows stale values to be read by the L0 cache. This can cause
incorrect behaviour when executing LL/SC based mutexes. This
patch ensures that all invalidates to SM states are exposed to
the L0 cache.

Change-Id: I7fefabdaa8027fdfa4c9c362abd7e467493196aa
---
M src/mem/ruby/protocol/MESI_Three_Level-L1cache.sm
1 file changed, 2 insertions(+), 2 deletions(-)



diff --git a/src/mem/ruby/protocol/MESI_Three_Level-L1cache.sm  
b/src/mem/ruby/protocol/MESI_Three_Level-L1cache.sm

index 00d897a..de82635 100644
--- a/src/mem/ruby/protocol/MESI_Three_Level-L1cache.sm
+++ b/src/mem/ruby/protocol/MESI_Three_Level-L1cache.sm
@@ -996,7 +996,7 @@
   }

   // Transitions from IM
-  transition({IM,SM}, Inv, IM) {
+  transition(IM, Inv, IM) {
 fi_sendInvAck;
 l_popL2RequestQueue;
   }
@@ -1029,7 +1029,7 @@
 kd_wakeUpDependents;
   }

-  transition(SM, L0_Invalidate_Else, SM_IL0) {
+  transition(SM, {Inv,L0_Invalidate_Else}, SM_IL0) {
 forward_eviction_to_L0_else;
   }


--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/28047
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I7fefabdaa8027fdfa4c9c362abd7e467493196aa
Gerrit-Change-Number: 28047
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Timothy Hayes 
Gerrit-MessageType: newchange
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