[gem5-dev] Change in gem5/gem5[develop]: python: Remove incorrect usage of typing 'Optional'
Bobby R. Bruce has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/52143 ) Change subject: python: Remove incorrect usage of typing 'Optional' .. python: Remove incorrect usage of typing 'Optional' There has been some confusion about usage of 'Optional'. In some areas of the codebase it was assumed this specifies an optional parameter (i.e., one which may or may not set, as it has a default value). This is incorrect. 'Optional[]' is shorthand for 'Union[, None]', i.e., it is used to state the value may be 'None'. This patch corrects this throughout the gem5 codebase. Change-Id: I77a6708dee448e8480870d073e128aed3d6ae904 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52143 Reviewed-by: Jason Lowe-Power Maintainer: Jason Lowe-Power Tested-by: kokoro --- M tests/gem5/x86-boot-tests/test_linux_boot.py M src/python/gem5/utils/requires.py M src/python/gem5/resources/downloader.py M src/python/gem5/components/cachehierarchies/classic/no_cache.py M src/python/gem5/resources/resource.py M src/python/gem5/components/cachehierarchies/classic/caches/l1dcache.py M src/python/gem5/components/cachehierarchies/classic/caches/l1icache.py M src/python/gem5/components/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py M src/python/gem5/components/cachehierarchies/classic/caches/mmu_cache.py M src/python/gem5/components/boards/x86_board.py M src/python/gem5/components/cachehierarchies/classic/caches/l2cache.py M src/python/gem5/components/cachehierarchies/classic/private_l1_cache_hierarchy.py 12 files changed, 63 insertions(+), 54 deletions(-) Approvals: Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved kokoro: Regressions pass diff --git a/src/python/gem5/components/boards/x86_board.py b/src/python/gem5/components/boards/x86_board.py index 49bf789..df7e7fb 100644 --- a/src/python/gem5/components/boards/x86_board.py +++ b/src/python/gem5/components/boards/x86_board.py @@ -271,7 +271,7 @@ kernel: AbstractResource, disk_image: AbstractResource, command: Optional[str] = None, -kernel_args: Optional[List[str]] = [], +kernel_args: List[str] = [], ): """Setup the full system files diff --git a/src/python/gem5/components/cachehierarchies/classic/caches/l1dcache.py b/src/python/gem5/components/cachehierarchies/classic/caches/l1dcache.py index 7346e7a..c80032b 100644 --- a/src/python/gem5/components/cachehierarchies/classic/caches/l1dcache.py +++ b/src/python/gem5/components/cachehierarchies/classic/caches/l1dcache.py @@ -28,7 +28,7 @@ from m5.objects import Cache, BasePrefetcher, StridePrefetcher -from typing import Optional, Type +from typing import Type class L1DCache(Cache): @@ -39,13 +39,13 @@ def __init__( self, size: str, -assoc: Optional[int] = 8, -tag_latency: Optional[int] = 1, -data_latency: Optional[int] = 1, -response_latency: Optional[int] = 1, -mshrs: Optional[int] = 16, -tgts_per_mshr: Optional[int] = 20, -writeback_clean: Optional[bool] = True, +assoc: int = 8, +tag_latency: int = 1, +data_latency: int = 1, +response_latency: int = 1, +mshrs: int = 16, +tgts_per_mshr: int = 20, +writeback_clean: bool = True, PrefetcherCls: Type[BasePrefetcher] = StridePrefetcher, ): super(L1DCache, self).__init__() diff --git a/src/python/gem5/components/cachehierarchies/classic/caches/l1icache.py b/src/python/gem5/components/cachehierarchies/classic/caches/l1icache.py index d1bf5aa..8e4ba09 100644 --- a/src/python/gem5/components/cachehierarchies/classic/caches/l1icache.py +++ b/src/python/gem5/components/cachehierarchies/classic/caches/l1icache.py @@ -24,7 +24,7 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from typing import Optional, Type +from typing import Type from m5.objects import Cache, BasePrefetcher, StridePrefetcher @@ -39,13 +39,13 @@ def __init__( self, size: str, -assoc: Optional[int] = 8, -tag_latency: Optional[int] = 1, -data_latency: Optional[int] = 1, -response_latency: Optional[int] = 1, -mshrs: Optional[int] = 16, -tgts_per_mshr: Optional[int] = 20, -writeback_clean: Optional[bool] = True, +assoc: int = 8, +tag_latency: int = 1, +data_latency: int = 1, +response_latency: int = 1, +mshrs: int = 16, +tgts_per_mshr: int = 20, +writeback_clean: bool = True, PrefetcherCls: Type[BasePrefetcher] = StridePrefetcher, ): super(L1ICache, self).__init__() diff --git a/src/python/gem5/components/cachehierarchies/classic/caches/l2cache.py
[gem5-dev] Change in gem5/gem5[develop]: python: Remove incorrect usage of typing 'Optional'
Bobby R. Bruce has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/52143 ) Change subject: python: Remove incorrect usage of typing 'Optional' .. python: Remove incorrect usage of typing 'Optional' There has been some confusion about usage of 'Optional'. In some areas of the codebase it was assumed this specifies an optional parameter (i.e., one which may or may not set, as it has a default value). This is incorrect. 'Optional[]' is shorthand for 'Union[, None]', i.e., it is used to state the value may be 'None'. This patch corrects this throughout the gem5 codebase. Change-Id: I77a6708dee448e8480870d073e128aed3d6ae904 --- M tests/gem5/x86-boot-tests/test_linux_boot.py M src/python/gem5/utils/requires.py M src/python/gem5/resources/downloader.py M src/python/gem5/components/cachehierarchies/classic/no_cache.py M src/python/gem5/resources/resource.py M src/python/gem5/components/cachehierarchies/classic/caches/l1dcache.py M src/python/gem5/components/cachehierarchies/classic/caches/l1icache.py M src/python/gem5/components/cachehierarchies/classic/private_l1_private_l2_cache_hierarchy.py M src/python/gem5/components/cachehierarchies/classic/caches/mmu_cache.py M src/python/gem5/components/boards/x86_board.py M src/python/gem5/components/cachehierarchies/classic/caches/l2cache.py M src/python/gem5/components/cachehierarchies/classic/private_l1_cache_hierarchy.py 12 files changed, 59 insertions(+), 54 deletions(-) diff --git a/src/python/gem5/components/boards/x86_board.py b/src/python/gem5/components/boards/x86_board.py index e766c3e..2338acca 100644 --- a/src/python/gem5/components/boards/x86_board.py +++ b/src/python/gem5/components/boards/x86_board.py @@ -275,7 +275,7 @@ kernel: AbstractResource, disk_image: AbstractResource, command: Optional[str] = None, -kernel_args: Optional[List[str]] = [], +kernel_args: List[str] = [], ): """Setup the full system files diff --git a/src/python/gem5/components/cachehierarchies/classic/caches/l1dcache.py b/src/python/gem5/components/cachehierarchies/classic/caches/l1dcache.py index 7346e7a..c80032b 100644 --- a/src/python/gem5/components/cachehierarchies/classic/caches/l1dcache.py +++ b/src/python/gem5/components/cachehierarchies/classic/caches/l1dcache.py @@ -28,7 +28,7 @@ from m5.objects import Cache, BasePrefetcher, StridePrefetcher -from typing import Optional, Type +from typing import Type class L1DCache(Cache): @@ -39,13 +39,13 @@ def __init__( self, size: str, -assoc: Optional[int] = 8, -tag_latency: Optional[int] = 1, -data_latency: Optional[int] = 1, -response_latency: Optional[int] = 1, -mshrs: Optional[int] = 16, -tgts_per_mshr: Optional[int] = 20, -writeback_clean: Optional[bool] = True, +assoc: int = 8, +tag_latency: int = 1, +data_latency: int = 1, +response_latency: int = 1, +mshrs: int = 16, +tgts_per_mshr: int = 20, +writeback_clean: bool = True, PrefetcherCls: Type[BasePrefetcher] = StridePrefetcher, ): super(L1DCache, self).__init__() diff --git a/src/python/gem5/components/cachehierarchies/classic/caches/l1icache.py b/src/python/gem5/components/cachehierarchies/classic/caches/l1icache.py index d1bf5aa..8e4ba09 100644 --- a/src/python/gem5/components/cachehierarchies/classic/caches/l1icache.py +++ b/src/python/gem5/components/cachehierarchies/classic/caches/l1icache.py @@ -24,7 +24,7 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from typing import Optional, Type +from typing import Type from m5.objects import Cache, BasePrefetcher, StridePrefetcher @@ -39,13 +39,13 @@ def __init__( self, size: str, -assoc: Optional[int] = 8, -tag_latency: Optional[int] = 1, -data_latency: Optional[int] = 1, -response_latency: Optional[int] = 1, -mshrs: Optional[int] = 16, -tgts_per_mshr: Optional[int] = 20, -writeback_clean: Optional[bool] = True, +assoc: int = 8, +tag_latency: int = 1, +data_latency: int = 1, +response_latency: int = 1, +mshrs: int = 16, +tgts_per_mshr: int = 20, +writeback_clean: bool = True, PrefetcherCls: Type[BasePrefetcher] = StridePrefetcher, ): super(L1ICache, self).__init__() diff --git a/src/python/gem5/components/cachehierarchies/classic/caches/l2cache.py b/src/python/gem5/components/cachehierarchies/classic/caches/l2cache.py index f3d7c14..b326255 100644 --- a/src/python/gem5/components/cachehierarchies/classic/caches/l2cache.py +++ b/src/python/gem5/components/cachehierarchies/classic/caches/l2cache.py @@ -28,7 +28,7 @@
