[gem5-dev] Change in gem5/gem5[develop]: sim: Remove the byte_order parameter from System.

2021-11-17 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/52106 )


 (

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the  
submitted one.

 )Change subject: sim: Remove the byte_order parameter from System.
..

sim: Remove the byte_order parameter from System.

Instead, get the byte order from the workload. The workload has a better
idea what the byte order should be, for instance based on what software
it's loaded or how the hardware was configured, and this gets rid of a
use of TARGET_ISA which was setting a default endianness.

Change-Id: Ic5d8a6f69a664957c4f837e3799ff93397ccfc64
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52106
Tested-by: kokoro 
Maintainer: Gabe Black 
Reviewed-by: Andreas Sandberg 
---
M src/sim/system.hh
M src/sim/System.py
2 files changed, 19 insertions(+), 9 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved
  Gabe Black: Looks good to me, approved
  kokoro: Regressions pass




diff --git a/src/sim/System.py b/src/sim/System.py
index 115fb94..596e25c 100644
--- a/src/sim/System.py
+++ b/src/sim/System.py
@@ -49,11 +49,6 @@
 class MemoryMode(Enum): vals = ['invalid', 'atomic', 'timing',
 'atomic_noncaching']

-if buildEnv['TARGET_ISA'] in ('sparc', 'power'):
-default_byte_order = 'big'
-else:
-default_byte_order = 'little'
-
 class System(SimObject):
 type = 'System'
 cxx_header = "sim/system.hh"
@@ -96,9 +91,6 @@

 cache_line_size = Param.Unsigned(64, "Cache line size in bytes")

-byte_order = Param.ByteOrder(default_byte_order,
- "Default byte order of system components")
-
 redirect_paths = VectorParam.RedirectPath([], "Path redirections")

 exit_on_work_items = Param.Bool(False, "Exit from the simulation loop  
when "

diff --git a/src/sim/system.hh b/src/sim/system.hh
index 7aeeea7..8f09b96 100644
--- a/src/sim/system.hh
+++ b/src/sim/system.hh
@@ -388,7 +388,7 @@
 ByteOrder
 getGuestByteOrder() const
 {
-return params().byte_order;
+return workload->byteOrder();
 }

 /**

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ic5d8a6f69a664957c4f837e3799ff93397ccfc64
Gerrit-Change-Number: 52106
Gerrit-PatchSet: 10
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: sim: Remove the byte_order parameter from System.

2021-10-27 Thread Gabe Black (Gerrit) via gem5-dev
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/52106 )



Change subject: sim: Remove the byte_order parameter from System.
..

sim: Remove the byte_order parameter from System.

Instead, get the byte order from the workload. The workload has a better
idea what the byte order should be, for instance based on what software
it's loaded or how the hardware was configured, and this gets rid of a
use of TARGET_ISA which was setting a default endianness.

Change-Id: Ic5d8a6f69a664957c4f837e3799ff93397ccfc64
---
M src/sim/system.hh
M src/sim/System.py
2 files changed, 15 insertions(+), 9 deletions(-)



diff --git a/src/sim/System.py b/src/sim/System.py
index 115fb94..596e25c 100644
--- a/src/sim/System.py
+++ b/src/sim/System.py
@@ -49,11 +49,6 @@
 class MemoryMode(Enum): vals = ['invalid', 'atomic', 'timing',
 'atomic_noncaching']

-if buildEnv['TARGET_ISA'] in ('sparc', 'power'):
-default_byte_order = 'big'
-else:
-default_byte_order = 'little'
-
 class System(SimObject):
 type = 'System'
 cxx_header = "sim/system.hh"
@@ -96,9 +91,6 @@

 cache_line_size = Param.Unsigned(64, "Cache line size in bytes")

-byte_order = Param.ByteOrder(default_byte_order,
- "Default byte order of system components")
-
 redirect_paths = VectorParam.RedirectPath([], "Path redirections")

 exit_on_work_items = Param.Bool(False, "Exit from the simulation loop  
when "

diff --git a/src/sim/system.hh b/src/sim/system.hh
index 7aeeea7..8f09b96 100644
--- a/src/sim/system.hh
+++ b/src/sim/system.hh
@@ -388,7 +388,7 @@
 ByteOrder
 getGuestByteOrder() const
 {
-return params().byte_order;
+return workload->byteOrder();
 }

 /**

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/52106
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ic5d8a6f69a664957c4f837e3799ff93397ccfc64
Gerrit-Change-Number: 52106
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black 
Gerrit-MessageType: newchange
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