[gem5-dev] Change in gem5/gem5[master]: arch-arm: adding register control flags enabling LSE implementation
Jordi Vaquero has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/19809 )
Change subject: arch-arm: adding register control flags enabling LSE
implementation
..
arch-arm: adding register control flags enabling LSE implementation
Added changes on arch-arm architecture to accept Atomic instructions
following ARM v8.1 documentation. That includes enabling atomic bit
in ID registers and add have_lse variable into arm system.
Change-Id: Ic28d3215d74ff129142fb51cb2fa217d3b1482de
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19809
Reviewed-by: Giacomo Travaglini
Maintainer: Giacomo Travaglini
Tested-by: kokoro
---
M src/arch/arm/ArmSystem.py
M src/arch/arm/isa.cc
M src/arch/arm/isa.hh
M src/arch/arm/system.cc
M src/arch/arm/system.hh
5 files changed, 20 insertions(+), 0 deletions(-)
Approvals:
Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py
index daf94a9..a92ae4f 100644
--- a/src/arch/arm/ArmSystem.py
+++ b/src/arch/arm/ArmSystem.py
@@ -86,6 +86,8 @@
"True if SVE is implemented (ARMv8)")
sve_vl = Param.SveVectorLength(1,
"SVE vector length in quadwords (128-bit)")
+have_lse = Param.Bool(True,
+"True if LSE is implemented (ARMv8.1)")
have_pan = Param.Bool(True,
"True if Priviledge Access Never is implemented (ARMv8.1)")
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 23738c6..299698d 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -93,6 +93,7 @@
haveSVE = system->haveSVE();
havePAN = system->havePAN();
sveVL = system->sveVL();
+haveLSE = system->haveLSE();
} else {
highestELIs64 = true; // ArmSystem::highestELIs64 does the same
haveSecurity = haveLPAE = haveVirtualization = false;
@@ -102,6 +103,7 @@
haveSVE = true;
havePAN = false;
sveVL = p->sve_vl_se;
+haveLSE = true;
}
// Initial rename mode depends on highestEL
@@ -393,6 +395,10 @@
miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits(
miscRegs[MISCREG_ID_AA64ISAR0_EL1], 19, 4,
haveCrypto ? 0x1112 : 0x0);
+// LSE
+miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits(
+miscRegs[MISCREG_ID_AA64ISAR0_EL1], 23, 20,
+haveLSE ? 0x2 : 0x0);
// PAN
miscRegs[MISCREG_ID_AA64MMFR1_EL1] = insertBits(
miscRegs[MISCREG_ID_AA64MMFR1_EL1], 23, 20,
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 63051cd..5e337c2 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -95,6 +95,7 @@
bool haveGICv3CPUInterface;
uint8_t physAddrRange;
bool haveSVE;
+bool haveLSE;
bool havePAN;
/** SVE vector length in quadwords */
@@ -687,6 +688,7 @@
SERIALIZE_SCALAR(physAddrRange);
SERIALIZE_SCALAR(haveSVE);
SERIALIZE_SCALAR(sveVL);
+SERIALIZE_SCALAR(haveLSE);
SERIALIZE_SCALAR(havePAN);
}
void unserialize(CheckpointIn )
@@ -704,6 +706,7 @@
UNSERIALIZE_SCALAR(physAddrRange);
UNSERIALIZE_SCALAR(haveSVE);
UNSERIALIZE_SCALAR(sveVL);
+UNSERIALIZE_SCALAR(haveLSE);
UNSERIALIZE_SCALAR(havePAN);
}
diff --git a/src/arch/arm/system.cc b/src/arch/arm/system.cc
index 874e3b0..4ea0d1a 100644
--- a/src/arch/arm/system.cc
+++ b/src/arch/arm/system.cc
@@ -73,6 +73,7 @@
_haveLargeAsid64(p->have_large_asid_64),
_haveSVE(p->have_sve),
_sveVL(p->sve_vl),
+ _haveLSE(p->have_lse),
_havePAN(p->have_pan),
_m5opRange(p->m5ops_base ?
RangeSize(p->m5ops_base, 0x1) :
diff --git a/src/arch/arm/system.hh b/src/arch/arm/system.hh
index e09f477..46c58e8 100644
--- a/src/arch/arm/system.hh
+++ b/src/arch/arm/system.hh
@@ -130,6 +130,11 @@
/** SVE vector length at reset, in quadwords */
const unsigned _sveVL;
+/**
+ * True if LSE is implemented (ARMv8.1)
+ */
+const bool _haveLSE;
+
/** True if Priviledge Access Never is implemented */
const unsigned _havePAN;
@@ -244,6 +249,9 @@
/** Returns the SVE vector length at reset, in quadwords */
unsigned sveVL() const { return _sveVL; }
+/** Returns true if LSE is implemented (ARMv8.1) */
+bool haveLSE() const { return _haveLSE; }
+
/** Returns true if Priviledge Access Never is implemented */
bool havePAN() const { return _havePAN; }
--
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Gerrit-Branch: master
Gerrit-Change-Id: Ic28d3215d74ff129142fb51cb2fa217d3b1482de
Gerrit-Change-Number:
[gem5-dev] Change in gem5/gem5[master]: arch-arm: adding register control flags enabling LSE implementation
Hello Andreas Sandberg, kokoro, I'd like you to reexamine a change. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/19809 to look at the new patch set (#3). Change subject: arch-arm: adding register control flags enabling LSE implementation .. arch-arm: adding register control flags enabling LSE implementation Added changes on arch-arm architecture to accept Atomic instructions following ARM v8.1 documentation. That includes enabling atomic bit in ID registers and add have_lse variable into arm system. Change-Id: Ic28d3215d74ff129142fb51cb2fa217d3b1482de --- M src/arch/arm/ArmSystem.py M src/arch/arm/isa.cc M src/arch/arm/isa.hh M src/arch/arm/system.cc M src/arch/arm/system.hh 5 files changed, 20 insertions(+), 0 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/19809 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Ic28d3215d74ff129142fb51cb2fa217d3b1482de Gerrit-Change-Number: 19809 Gerrit-PatchSet: 3 Gerrit-Owner: Jordi Vaquero Gerrit-Reviewer: Andreas Sandberg Gerrit-Reviewer: kokoro Gerrit-CC: Giacomo Travaglini Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: arch-arm: adding register control flags enabling LSE implementation
Jordi Vaquero has uploaded a new patch set (#2). ( https://gem5-review.googlesource.com/c/public/gem5/+/19848 ) Change subject: arch-arm: adding register control flags enabling LSE implementation .. arch-arm: adding register control flags enabling LSE implementation Added changes on arch-arm architecture to accept Atomic instructions following ARM v8.1 documentation. That includes enabling atomic bit in ID registers and add have_lse variable into arm system. Change-Id: I79c65170f9a4dbc317041f987897444c025fb536 --- M src/arch/arm/ArmSystem.py M src/arch/arm/isa.cc M src/arch/arm/isa.hh M src/arch/arm/system.cc M src/arch/arm/system.hh 5 files changed, 20 insertions(+), 0 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/19848 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: I79c65170f9a4dbc317041f987897444c025fb536 Gerrit-Change-Number: 19848 Gerrit-PatchSet: 2 Gerrit-Owner: Jordi Vaquero Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: arch-arm: adding register control flags enabling LSE implementation
Jordi Vaquero has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/19848 )
Change subject: arch-arm: adding register control flags enabling LSE
implementation
..
arch-arm: adding register control flags enabling LSE implementation
Added changes on arch-arm architecture to accept Atomic instructions
following ARM v8.1 documentation. That includes enabling atomic bit
in control registers and add have_lse variable into arm system.
Change-Id: I79c65170f9a4dbc317041f987897444c025fb536
---
M src/arch/arm/ArmSystem.py
M src/arch/arm/isa.cc
M src/arch/arm/isa.hh
M src/arch/arm/system.cc
M src/arch/arm/system.hh
5 files changed, 20 insertions(+), 0 deletions(-)
diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py
index daf94a9..a92ae4f 100644
--- a/src/arch/arm/ArmSystem.py
+++ b/src/arch/arm/ArmSystem.py
@@ -86,6 +86,8 @@
"True if SVE is implemented (ARMv8)")
sve_vl = Param.SveVectorLength(1,
"SVE vector length in quadwords (128-bit)")
+have_lse = Param.Bool(True,
+"True if LSE is implemented (ARMv8.1)")
have_pan = Param.Bool(True,
"True if Priviledge Access Never is implemented (ARMv8.1)")
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 23738c6..299698d 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -93,6 +93,7 @@
haveSVE = system->haveSVE();
havePAN = system->havePAN();
sveVL = system->sveVL();
+haveLSE = system->haveLSE();
} else {
highestELIs64 = true; // ArmSystem::highestELIs64 does the same
haveSecurity = haveLPAE = haveVirtualization = false;
@@ -102,6 +103,7 @@
haveSVE = true;
havePAN = false;
sveVL = p->sve_vl_se;
+haveLSE = true;
}
// Initial rename mode depends on highestEL
@@ -393,6 +395,10 @@
miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits(
miscRegs[MISCREG_ID_AA64ISAR0_EL1], 19, 4,
haveCrypto ? 0x1112 : 0x0);
+// LSE
+miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits(
+miscRegs[MISCREG_ID_AA64ISAR0_EL1], 23, 20,
+haveLSE ? 0x2 : 0x0);
// PAN
miscRegs[MISCREG_ID_AA64MMFR1_EL1] = insertBits(
miscRegs[MISCREG_ID_AA64MMFR1_EL1], 23, 20,
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 63051cd..5e337c2 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -95,6 +95,7 @@
bool haveGICv3CPUInterface;
uint8_t physAddrRange;
bool haveSVE;
+bool haveLSE;
bool havePAN;
/** SVE vector length in quadwords */
@@ -687,6 +688,7 @@
SERIALIZE_SCALAR(physAddrRange);
SERIALIZE_SCALAR(haveSVE);
SERIALIZE_SCALAR(sveVL);
+SERIALIZE_SCALAR(haveLSE);
SERIALIZE_SCALAR(havePAN);
}
void unserialize(CheckpointIn )
@@ -704,6 +706,7 @@
UNSERIALIZE_SCALAR(physAddrRange);
UNSERIALIZE_SCALAR(haveSVE);
UNSERIALIZE_SCALAR(sveVL);
+UNSERIALIZE_SCALAR(haveLSE);
UNSERIALIZE_SCALAR(havePAN);
}
diff --git a/src/arch/arm/system.cc b/src/arch/arm/system.cc
index 874e3b0..4ea0d1a 100644
--- a/src/arch/arm/system.cc
+++ b/src/arch/arm/system.cc
@@ -73,6 +73,7 @@
_haveLargeAsid64(p->have_large_asid_64),
_haveSVE(p->have_sve),
_sveVL(p->sve_vl),
+ _haveLSE(p->have_lse),
_havePAN(p->have_pan),
_m5opRange(p->m5ops_base ?
RangeSize(p->m5ops_base, 0x1) :
diff --git a/src/arch/arm/system.hh b/src/arch/arm/system.hh
index e09f477..46c58e8 100644
--- a/src/arch/arm/system.hh
+++ b/src/arch/arm/system.hh
@@ -130,6 +130,11 @@
/** SVE vector length at reset, in quadwords */
const unsigned _sveVL;
+/**
+ * True if LSE is implemented (ARMv8.1)
+ */
+const bool _haveLSE;
+
/** True if Priviledge Access Never is implemented */
const unsigned _havePAN;
@@ -244,6 +249,9 @@
/** Returns the SVE vector length at reset, in quadwords */
unsigned sveVL() const { return _sveVL; }
+/** Returns true if LSE is implemented (ARMv8.1) */
+bool haveLSE() const { return _haveLSE; }
+
/** Returns true if Priviledge Access Never is implemented */
bool havePAN() const { return _havePAN; }
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/19848
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: I79c65170f9a4dbc317041f987897444c025fb536
Gerrit-Change-Number: 19848
Gerrit-PatchSet: 1
Gerrit-Owner: Jordi Vaquero
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[master]: arch-arm: adding register control flags enabling LSE implementation
Jordi Vaquero has uploaded a new patch set (#2). ( https://gem5-review.googlesource.com/c/public/gem5/+/19809 ) Change subject: arch-arm: adding register control flags enabling LSE implementation .. arch-arm: adding register control flags enabling LSE implementation Added changes on arch-arm architecture to accept Atomic instructions following ARM v8.1 documentation. That includes enabling atomic bit in control registers and add have_lse variable into arm system. Change-Id: Ic28d3215d74ff129142fb51cb2fa217d3b1482de --- M src/arch/arm/ArmSystem.py M src/arch/arm/isa.cc M src/arch/arm/isa.hh M src/arch/arm/system.cc M src/arch/arm/system.hh 5 files changed, 20 insertions(+), 0 deletions(-) -- To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/19809 To unsubscribe, or for help writing mail filters, visit https://gem5-review.googlesource.com/settings Gerrit-Project: public/gem5 Gerrit-Branch: master Gerrit-Change-Id: Ic28d3215d74ff129142fb51cb2fa217d3b1482de Gerrit-Change-Number: 19809 Gerrit-PatchSet: 2 Gerrit-Owner: Jordi Vaquero Gerrit-CC: Giacomo Travaglini Gerrit-MessageType: newpatchset ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Change in gem5/gem5[master]: arch-arm: adding register control flags enabling LSE implementation
Jordi Vaquero has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/19809 )
Change subject: arch-arm: adding register control flags enabling LSE
implementation
..
arch-arm: adding register control flags enabling LSE implementation
Added changes on arch-arm architecture to accept Atomic instructions
following ARM v8.1 documentation. That includes enabling atomic bit
in contorl registers and add have_LSE variable into arm system.
Change-Id: Ic28d3215d74ff129142fb51cb2fa217d3b1482de
---
M src/arch/arm/ArmSystem.py
M src/arch/arm/isa.cc
M src/arch/arm/isa.hh
M src/arch/arm/system.cc
M src/arch/arm/system.hh
5 files changed, 20 insertions(+), 0 deletions(-)
diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py
index daf94a9..a92ae4f 100644
--- a/src/arch/arm/ArmSystem.py
+++ b/src/arch/arm/ArmSystem.py
@@ -86,6 +86,8 @@
"True if SVE is implemented (ARMv8)")
sve_vl = Param.SveVectorLength(1,
"SVE vector length in quadwords (128-bit)")
+have_lse = Param.Bool(True,
+"True if LSE is implemented (ARMv8.1)")
have_pan = Param.Bool(True,
"True if Priviledge Access Never is implemented (ARMv8.1)")
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 23738c6..299698d 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -93,6 +93,7 @@
haveSVE = system->haveSVE();
havePAN = system->havePAN();
sveVL = system->sveVL();
+haveLSE = system->haveLSE();
} else {
highestELIs64 = true; // ArmSystem::highestELIs64 does the same
haveSecurity = haveLPAE = haveVirtualization = false;
@@ -102,6 +103,7 @@
haveSVE = true;
havePAN = false;
sveVL = p->sve_vl_se;
+haveLSE = true;
}
// Initial rename mode depends on highestEL
@@ -393,6 +395,10 @@
miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits(
miscRegs[MISCREG_ID_AA64ISAR0_EL1], 19, 4,
haveCrypto ? 0x1112 : 0x0);
+// LSE
+miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits(
+miscRegs[MISCREG_ID_AA64ISAR0_EL1], 23, 20,
+haveLSE ? 0x2 : 0x0);
// PAN
miscRegs[MISCREG_ID_AA64MMFR1_EL1] = insertBits(
miscRegs[MISCREG_ID_AA64MMFR1_EL1], 23, 20,
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 63051cd..5e337c2 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -95,6 +95,7 @@
bool haveGICv3CPUInterface;
uint8_t physAddrRange;
bool haveSVE;
+bool haveLSE;
bool havePAN;
/** SVE vector length in quadwords */
@@ -687,6 +688,7 @@
SERIALIZE_SCALAR(physAddrRange);
SERIALIZE_SCALAR(haveSVE);
SERIALIZE_SCALAR(sveVL);
+SERIALIZE_SCALAR(haveLSE);
SERIALIZE_SCALAR(havePAN);
}
void unserialize(CheckpointIn )
@@ -704,6 +706,7 @@
UNSERIALIZE_SCALAR(physAddrRange);
UNSERIALIZE_SCALAR(haveSVE);
UNSERIALIZE_SCALAR(sveVL);
+UNSERIALIZE_SCALAR(haveLSE);
UNSERIALIZE_SCALAR(havePAN);
}
diff --git a/src/arch/arm/system.cc b/src/arch/arm/system.cc
index 874e3b0..4ea0d1a 100644
--- a/src/arch/arm/system.cc
+++ b/src/arch/arm/system.cc
@@ -73,6 +73,7 @@
_haveLargeAsid64(p->have_large_asid_64),
_haveSVE(p->have_sve),
_sveVL(p->sve_vl),
+ _haveLSE(p->have_lse),
_havePAN(p->have_pan),
_m5opRange(p->m5ops_base ?
RangeSize(p->m5ops_base, 0x1) :
diff --git a/src/arch/arm/system.hh b/src/arch/arm/system.hh
index e09f477..46c58e8 100644
--- a/src/arch/arm/system.hh
+++ b/src/arch/arm/system.hh
@@ -130,6 +130,11 @@
/** SVE vector length at reset, in quadwords */
const unsigned _sveVL;
+/**
+ * True if LSE is implemented (ARMv8.1)
+ */
+const bool _haveLSE;
+
/** True if Priviledge Access Never is implemented */
const unsigned _havePAN;
@@ -244,6 +249,9 @@
/** Returns the SVE vector length at reset, in quadwords */
unsigned sveVL() const { return _sveVL; }
+/** Returns true if LSE is implemented (ARMv8.1) */
+bool haveLSE() const { return _haveLSE; }
+
/** Returns true if Priviledge Access Never is implemented */
bool havePAN() const { return _havePAN; }
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/19809
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https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Ic28d3215d74ff129142fb51cb2fa217d3b1482de
Gerrit-Change-Number: 19809
Gerrit-PatchSet: 1
Gerrit-Owner: Jordi Vaquero
Gerrit-MessageType: newchange
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