[gem5-dev] Change in gem5/gem5[master]: sparc: Move translation constants from isa_traits.hh into tlb.hh.

2019-04-30 Thread Gabe Black (Gerrit)
Gabe Black has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/c/public/gem5/+/18470 )


Change subject: sparc: Move translation constants from isa_traits.hh into  
tlb.hh.

..

sparc: Move translation constants from isa_traits.hh into tlb.hh.

These aren't used outside of SPARC. Also get rid of some unused
constants.

Change-Id: Icfe119f88189348245a6f225a61e62dfa93ea951
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18470
Reviewed-by: Gabe Black 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M src/arch/sparc/isa_traits.hh
M src/arch/sparc/tlb.hh
2 files changed, 5 insertions(+), 12 deletions(-)

Approvals:
  Gabe Black: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/sparc/isa_traits.hh b/src/arch/sparc/isa_traits.hh
index 5bcfc04..f42cdb9 100644
--- a/src/arch/sparc/isa_traits.hh
+++ b/src/arch/sparc/isa_traits.hh
@@ -44,23 +44,11 @@
 // This makes sure the big endian versions of certain functions are used.
 using namespace BigEndianGuest;

-// real address virtual mapping
-// sort of like alpha super page, but less frequently used
-const Addr SegKPMEnd  = ULL(0xfffc);
-const Addr SegKPMBase = ULL(0xfac0);
-
 const Addr PageShift = 13;
 const Addr PageBytes = ULL(1) << PageShift;

 StaticInstPtr decodeInst(ExtMachInst);

-/// TLB Stuff 
-const Addr StartVAddrHole = ULL(0x8000);
-const Addr EndVAddrHole = ULL(0x7FFF);
-const Addr VAddrAMask = ULL(0x);
-const Addr PAddrImplMask = ULL(0x00FF);
-const Addr BytesInPageMask = ULL(0x1FFF);
-
 // Memory accesses cannot be unaligned
 const bool HasUnalignedMemAcc = false;

diff --git a/src/arch/sparc/tlb.hh b/src/arch/sparc/tlb.hh
index e5e6753..0d173da 100644
--- a/src/arch/sparc/tlb.hh
+++ b/src/arch/sparc/tlb.hh
@@ -44,6 +44,11 @@
 namespace SparcISA
 {

+const Addr StartVAddrHole = ULL(0x8000);
+const Addr EndVAddrHole = ULL(0x7FFF);
+const Addr VAddrAMask = ULL(0x);
+const Addr PAddrImplMask = ULL(0x00FF);
+
 class TLB : public BaseTLB
 {
 // These faults need to be able to populate the tlb in SE mode.

--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Icfe119f88189348245a6f225a61e62dfa93ea951
Gerrit-Change-Number: 18470
Gerrit-PatchSet: 2
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[master]: sparc: Move translation constants from isa_traits.hh into tlb.hh.

2019-04-29 Thread Gabe Black (Gerrit)
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/18470



Change subject: sparc: Move translation constants from isa_traits.hh into  
tlb.hh.

..

sparc: Move translation constants from isa_traits.hh into tlb.hh.

These aren't used outside of SPARC. Also get rid of some unused
constants.

Change-Id: Icfe119f88189348245a6f225a61e62dfa93ea951
---
M src/arch/sparc/isa_traits.hh
M src/arch/sparc/tlb.hh
2 files changed, 5 insertions(+), 12 deletions(-)



diff --git a/src/arch/sparc/isa_traits.hh b/src/arch/sparc/isa_traits.hh
index 5bcfc04..f42cdb9 100644
--- a/src/arch/sparc/isa_traits.hh
+++ b/src/arch/sparc/isa_traits.hh
@@ -44,23 +44,11 @@
 // This makes sure the big endian versions of certain functions are used.
 using namespace BigEndianGuest;

-// real address virtual mapping
-// sort of like alpha super page, but less frequently used
-const Addr SegKPMEnd  = ULL(0xfffc);
-const Addr SegKPMBase = ULL(0xfac0);
-
 const Addr PageShift = 13;
 const Addr PageBytes = ULL(1) << PageShift;

 StaticInstPtr decodeInst(ExtMachInst);

-/// TLB Stuff 
-const Addr StartVAddrHole = ULL(0x8000);
-const Addr EndVAddrHole = ULL(0x7FFF);
-const Addr VAddrAMask = ULL(0x);
-const Addr PAddrImplMask = ULL(0x00FF);
-const Addr BytesInPageMask = ULL(0x1FFF);
-
 // Memory accesses cannot be unaligned
 const bool HasUnalignedMemAcc = false;

diff --git a/src/arch/sparc/tlb.hh b/src/arch/sparc/tlb.hh
index e5e6753..0d173da 100644
--- a/src/arch/sparc/tlb.hh
+++ b/src/arch/sparc/tlb.hh
@@ -44,6 +44,11 @@
 namespace SparcISA
 {

+const Addr StartVAddrHole = ULL(0x8000);
+const Addr EndVAddrHole = ULL(0x7FFF);
+const Addr VAddrAMask = ULL(0x);
+const Addr PAddrImplMask = ULL(0x00FF);
+
 class TLB : public BaseTLB
 {
 // These faults need to be able to populate the tlb in SE mode.

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/18470
To unsubscribe, or for help writing mail filters, visit  
https://gem5-review.googlesource.com/settings


Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: Icfe119f88189348245a6f225a61e62dfa93ea951
Gerrit-Change-Number: 18470
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black 
Gerrit-MessageType: newchange
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