[gem5-dev] Change in gem5/gem5[master]: x86: Add a ld/st microop flag for marking an access uncacheable.

2018-05-02 Thread Gabe Black (Gerrit) 
Gabe Black has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/9881 )


Change subject: x86: Add a ld/st microop flag for marking an access  
uncacheable.

..

x86: Add a ld/st microop flag for marking an access uncacheable.

This percolates down to the memory request object which will have its
"UNCACHEABLE" flag set.

Change-Id: Ie73f4249bfcd57f45a473f220d0988856715a9ce
Reviewed-on: https://gem5-review.googlesource.com/9881
Reviewed-by: Anthony Gutierrez 
Reviewed-by: Jason Lowe-Power 
Maintainer: Anthony Gutierrez 
---
M src/arch/x86/isa/microops/ldstop.isa
1 file changed, 22 insertions(+), 15 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, but someone else must approve
  Anthony Gutierrez: Looks good to me, approved; Looks good to me, approved



diff --git a/src/arch/x86/isa/microops/ldstop.isa  
b/src/arch/x86/isa/microops/ldstop.isa

index 83e24e1..60c6d29 100644
--- a/src/arch/x86/isa/microops/ldstop.isa
+++ b/src/arch/x86/isa/microops/ldstop.isa
@@ -295,7 +295,7 @@
 class LdStOp(X86Microop):
 def __init__(self, data, segment, addr, disp,
 dataSize, addressSize, baseFlags, atCPL0, prefetch,  
nonSpec,

-implicitStack):
+implicitStack, uncacheable):
 self.data = data
 [self.scale, self.index, self.base] = addr
 self.disp = disp
@@ -311,6 +311,8 @@
 self.instFlags += " | (1ULL << StaticInst::IsDataPrefetch)"
 if nonSpec:
 self.instFlags += " | (1ULL <<  
StaticInst::IsNonSpeculative)"

+if uncacheable:
+self.instFlags += " | (Request::UNCACHEABLE)"
 # For implicit stack operations, we should use *not* use the
 # alternative addressing mode for loads/stores if the prefix  
is set

 if not implicitStack:
@@ -335,7 +337,7 @@
 class BigLdStOp(X86Microop):
 def __init__(self, data, segment, addr, disp,
 dataSize, addressSize, baseFlags, atCPL0, prefetch,  
nonSpec,

-implicitStack):
+implicitStack, uncacheable):
 self.data = data
 [self.scale, self.index, self.base] = addr
 self.disp = disp
@@ -351,6 +353,8 @@
 self.instFlags += " | (1ULL << StaticInst::IsDataPrefetch)"
 if nonSpec:
 self.instFlags += " | (1ULL <<  
StaticInst::IsNonSpeculative)"

+if uncacheable:
+self.instFlags += " | (Request::UNCACHEABLE)"
 # For implicit stack operations, we should use *not* use the
 # alternative addressing mode for loads/stores if the prefix  
is set

 if not implicitStack:
@@ -383,10 +387,10 @@
 class LdStSplitOp(LdStOp):
 def __init__(self, data, segment, addr, disp,
 dataSize, addressSize, baseFlags, atCPL0, prefetch,  
nonSpec,

-implicitStack):
+implicitStack, uncacheable):
 super(LdStSplitOp, self).__init__(0, segment, addr, disp,
 dataSize, addressSize, baseFlags, atCPL0, prefetch,  
nonSpec,

-implicitStack)
+implicitStack, uncacheable)
 (self.dataLow, self.dataHi) = data

 def getAllocator(self, microFlags):
@@ -466,10 +470,10 @@
 dataSize="env.dataSize",
 addressSize=addressSize,
 atCPL0=False, prefetch=False, nonSpec=nonSpec,
-implicitStack=implicitStack):
+implicitStack=implicitStack, uncacheable=False):
 super(LoadOp, self).__init__(data, segment, addr,
 disp, dataSize, addressSize, mem_flags,
-atCPL0, prefetch, nonSpec, implicitStack)
+atCPL0, prefetch, nonSpec, implicitStack,  
uncacheable)

 self.className = Name
 self.mnemonic = name

@@ -547,10 +551,10 @@
 dataSize="env.dataSize",
 addressSize="env.addressSize",
 atCPL0=False, prefetch=False, nonSpec=nonSpec,
-implicitStack=False):
+implicitStack=False, uncacheable=False):
 super(LoadOp, self).__init__(data, segment, addr,
 disp, dataSize, addressSize, mem_flags,
-atCPL0, prefetch, nonSpec, implicitStack)
+atCPL0, prefetch, nonSpec, implicitStack,  
uncacheable)

 self.className = Name
 self.mnemonic = name

@@ -601,10 +605,11 @@
 def __init__(self, data, segment, addr, disp = 0,
 dataSize="env.dataSize",
 addressSize=addressSize,
-

[gem5-dev] Change in gem5/gem5[master]: x86: Add a ld/st microop flag for marking an access uncacheable.

2018-04-13 Thread Gabe Black (Gerrit) 
Gabe Black has uploaded this change for review. (  
https://gem5-review.googlesource.com/9881



Change subject: x86: Add a ld/st microop flag for marking an access  
uncacheable.

..

x86: Add a ld/st microop flag for marking an access uncacheable.

This percolates down to the memory request object which will have its
"UNCACHEABLE" flag set.

Change-Id: Ie73f4249bfcd57f45a473f220d0988856715a9ce
---
M src/arch/x86/isa/microops/ldstop.isa
1 file changed, 22 insertions(+), 15 deletions(-)



diff --git a/src/arch/x86/isa/microops/ldstop.isa  
b/src/arch/x86/isa/microops/ldstop.isa

index 83e24e1..60c6d29 100644
--- a/src/arch/x86/isa/microops/ldstop.isa
+++ b/src/arch/x86/isa/microops/ldstop.isa
@@ -295,7 +295,7 @@
 class LdStOp(X86Microop):
 def __init__(self, data, segment, addr, disp,
 dataSize, addressSize, baseFlags, atCPL0, prefetch,  
nonSpec,

-implicitStack):
+implicitStack, uncacheable):
 self.data = data
 [self.scale, self.index, self.base] = addr
 self.disp = disp
@@ -311,6 +311,8 @@
 self.instFlags += " | (1ULL << StaticInst::IsDataPrefetch)"
 if nonSpec:
 self.instFlags += " | (1ULL <<  
StaticInst::IsNonSpeculative)"

+if uncacheable:
+self.instFlags += " | (Request::UNCACHEABLE)"
 # For implicit stack operations, we should use *not* use the
 # alternative addressing mode for loads/stores if the prefix  
is set

 if not implicitStack:
@@ -335,7 +337,7 @@
 class BigLdStOp(X86Microop):
 def __init__(self, data, segment, addr, disp,
 dataSize, addressSize, baseFlags, atCPL0, prefetch,  
nonSpec,

-implicitStack):
+implicitStack, uncacheable):
 self.data = data
 [self.scale, self.index, self.base] = addr
 self.disp = disp
@@ -351,6 +353,8 @@
 self.instFlags += " | (1ULL << StaticInst::IsDataPrefetch)"
 if nonSpec:
 self.instFlags += " | (1ULL <<  
StaticInst::IsNonSpeculative)"

+if uncacheable:
+self.instFlags += " | (Request::UNCACHEABLE)"
 # For implicit stack operations, we should use *not* use the
 # alternative addressing mode for loads/stores if the prefix  
is set

 if not implicitStack:
@@ -383,10 +387,10 @@
 class LdStSplitOp(LdStOp):
 def __init__(self, data, segment, addr, disp,
 dataSize, addressSize, baseFlags, atCPL0, prefetch,  
nonSpec,

-implicitStack):
+implicitStack, uncacheable):
 super(LdStSplitOp, self).__init__(0, segment, addr, disp,
 dataSize, addressSize, baseFlags, atCPL0, prefetch,  
nonSpec,

-implicitStack)
+implicitStack, uncacheable)
 (self.dataLow, self.dataHi) = data

 def getAllocator(self, microFlags):
@@ -466,10 +470,10 @@
 dataSize="env.dataSize",
 addressSize=addressSize,
 atCPL0=False, prefetch=False, nonSpec=nonSpec,
-implicitStack=implicitStack):
+implicitStack=implicitStack, uncacheable=False):
 super(LoadOp, self).__init__(data, segment, addr,
 disp, dataSize, addressSize, mem_flags,
-atCPL0, prefetch, nonSpec, implicitStack)
+atCPL0, prefetch, nonSpec, implicitStack,  
uncacheable)

 self.className = Name
 self.mnemonic = name

@@ -547,10 +551,10 @@
 dataSize="env.dataSize",
 addressSize="env.addressSize",
 atCPL0=False, prefetch=False, nonSpec=nonSpec,
-implicitStack=False):
+implicitStack=False, uncacheable=False):
 super(LoadOp, self).__init__(data, segment, addr,
 disp, dataSize, addressSize, mem_flags,
-atCPL0, prefetch, nonSpec, implicitStack)
+atCPL0, prefetch, nonSpec, implicitStack,  
uncacheable)

 self.className = Name
 self.mnemonic = name

@@ -601,10 +605,11 @@
 def __init__(self, data, segment, addr, disp = 0,
 dataSize="env.dataSize",
 addressSize=addressSize,
-atCPL0=False, nonSpec=False,  
implicitStack=implicitStack):
+atCPL0=False, nonSpec=False,  
implicitStack=implicitStack,

+uncacheable=False):
 super(StoreOp, self).__init__(data, segment, addr, disp,
 dataSize, addressSize, mem_flags, atCPL0, False,
-nonSpec,