[gem5-dev] Change in gem5/gem5[master]: x86: Move miscreg initialization to the ISA class.
Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/24185 )
Change subject: x86: Move miscreg initialization to the ISA class.
..
x86: Move miscreg initialization to the ISA class.
The initCPU function was setting a lot of values to zero or other
initial values, but that's something the ISA object can do as part of
its clear() method. This gets rid of a lot of code that was
individually zeroing registers, and also centralizes responsibility
for those registers in the ISA.
Change-Id: Iafcffd3f9329c39f77009b38b1696f91c36c117e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24185
Reviewed-by: Gabe Black
Maintainer: Gabe Black
Tested-by: kokoro
---
M src/arch/x86/isa.cc
M src/arch/x86/utility.cc
2 files changed, 29 insertions(+), 106 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/x86/isa.cc b/src/arch/x86/isa.cc
index d96a858..6577240 100644
--- a/src/arch/x86/isa.cc
+++ b/src/arch/x86/isa.cc
@@ -108,8 +108,29 @@
// Blank everything. 0 might not be an appropriate value for some
things,
// but it is for most.
memset(regVal, 0, NumMiscRegs * sizeof(RegVal));
+
+// If some state should be non-zero after a reset, set those values
here.
+regVal[MISCREG_CR0] = 0x6010ULL;
+
+regVal[MISCREG_MTRRCAP] = 0x0508;
+
+regVal[MISCREG_MCG_CAP] = 0x104;
+
+regVal[MISCREG_PAT] = 0x0007040600070406ULL;
+
+regVal[MISCREG_SYSCFG] = 0x20601;
+
+regVal[MISCREG_TOP_MEM] = 0x400;
+
regVal[MISCREG_DR6] = (mask(8) << 4) | (mask(16) << 16);
regVal[MISCREG_DR7] = 1 << 10;
+
+LocalApicBase lApicBase = 0;
+lApicBase.base = 0xFEE0 >> 12;
+lApicBase.enable = 1;
+// The "bsp" bit will be set when this register is read, since then
we'll
+// have a ThreadContext to check the contextId from.
+regVal[MISCREG_APIC_BASE] = lApicBase;
}
ISA::ISA(Params *p)
@@ -148,6 +169,12 @@
return insertBits(fsw, 13, 11, top);
}
+if (miscReg == MISCREG_APIC_BASE) {
+LocalApicBase base = regVal[MISCREG_APIC_BASE];
+base.bsp = (tc->contextId() == 0);
+return base;
+}
+
return readMiscRegNoEffect(miscReg);
}
diff --git a/src/arch/x86/utility.cc b/src/arch/x86/utility.cc
index b430124..13019e9 100644
--- a/src/arch/x86/utility.cc
+++ b/src/arch/x86/utility.cc
@@ -71,7 +71,8 @@
}
}
-void initCPU(ThreadContext *tc, int cpuId)
+void
+initCPU(ThreadContext *tc, int cpuId)
{
// This function is essentially performing a reset. The actual INIT
// interrupt does a subset of this, so we'll piggyback on some of its
@@ -79,109 +80,11 @@
InitInterrupt init(0);
init.invoke(tc);
-PCState pc = tc->pcState();
-pc.upc(0);
-pc.nupc(1);
-tc->pcState(pc);
-
-// These next two loops zero internal microcode and implicit registers.
-// They aren't specified by the ISA but are used internally by M5's
-// implementation.
-for (int index = 0; index < NumMicroIntRegs; index++) {
-tc->setIntReg(INTREG_MICRO(index), 0);
-}
-
-for (int index = 0; index < NumImplicitIntRegs; index++) {
-tc->setIntReg(INTREG_IMPLICIT(index), 0);
-}
-
// Set integer register EAX to 0 to indicate that the optional BIST
// passed. No BIST actually runs, but software may still check this
// register for errors.
tc->setIntReg(INTREG_RAX, 0);
-tc->setMiscReg(MISCREG_CR0, 0x6010ULL);
-tc->setMiscReg(MISCREG_CR8, 0);
-
-// TODO initialize x87, 64 bit, and 128 bit media state
-
-tc->setMiscReg(MISCREG_MTRRCAP, 0x0508);
-for (int i = 0; i < 8; i++) {
-tc->setMiscReg(MISCREG_MTRR_PHYS_BASE(i), 0);
-tc->setMiscReg(MISCREG_MTRR_PHYS_MASK(i), 0);
-}
-tc->setMiscReg(MISCREG_MTRR_FIX_64K_0, 0);
-tc->setMiscReg(MISCREG_MTRR_FIX_16K_8, 0);
-tc->setMiscReg(MISCREG_MTRR_FIX_16K_A, 0);
-tc->setMiscReg(MISCREG_MTRR_FIX_4K_C, 0);
-tc->setMiscReg(MISCREG_MTRR_FIX_4K_C8000, 0);
-tc->setMiscReg(MISCREG_MTRR_FIX_4K_D, 0);
-tc->setMiscReg(MISCREG_MTRR_FIX_4K_D8000, 0);
-tc->setMiscReg(MISCREG_MTRR_FIX_4K_E, 0);
-tc->setMiscReg(MISCREG_MTRR_FIX_4K_E8000, 0);
-tc->setMiscReg(MISCREG_MTRR_FIX_4K_F, 0);
-tc->setMiscReg(MISCREG_MTRR_FIX_4K_F8000, 0);
-
-tc->setMiscReg(MISCREG_DEF_TYPE, 0);
-
-tc->setMiscReg(MISCREG_MCG_CAP, 0x104);
-tc->setMiscReg(MISCREG_MCG_STATUS, 0);
-tc->setMiscReg(MISCREG_MCG_CTL, 0);
-
-for (int i = 0; i < 5; i++) {
-tc->setMiscReg(MISCREG_MC_CTL(i), 0);
-tc->setMiscReg(MISCREG_MC_STATUS(i), 0);
-tc->setMiscReg(MISCREG_MC_ADDR(i), 0);
-tc->setMiscReg(MISCREG_MC_MISC(i), 0);
-}
-
-tc->setMiscReg(MISCREG_TSC, 0);
-
[gem5-dev] Change in gem5/gem5[master]: x86: Move miscreg initialization to the ISA class.
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/24185 )
Change subject: x86: Move miscreg initialization to the ISA class.
..
x86: Move miscreg initialization to the ISA class.
The initCPU function was setting a lot of values to zero or other
initial values, but that's something the ISA object can do as part of
its clear() method. This gets rid of a lot of code that was
individually zeroing registers, and also centralizes responsibility
for those registers in the ISA.
Change-Id: Iafcffd3f9329c39f77009b38b1696f91c36c117e
---
M src/arch/x86/isa.cc
M src/arch/x86/utility.cc
2 files changed, 28 insertions(+), 106 deletions(-)
diff --git a/src/arch/x86/isa.cc b/src/arch/x86/isa.cc
index d96a858..582cbb2 100644
--- a/src/arch/x86/isa.cc
+++ b/src/arch/x86/isa.cc
@@ -108,8 +108,28 @@
// Blank everything. 0 might not be an appropriate value for some
things,
// but it is for most.
memset(regVal, 0, NumMiscRegs * sizeof(RegVal));
+
+regVal[MISCREG_CR0] = 0x6010ULL;
+
+regVal[MISCREG_MTRRCAP] = 0x0508;
+
+regVal[MISCREG_MCG_CAP] = 0x104;
+
+regVal[MISCREG_PAT] = 0x0007040600070406ULL;
+
+regVal[MISCREG_SYSCFG] = 0x20601;
+
+regVal[MISCREG_TOP_MEM] = 0x400;
+
regVal[MISCREG_DR6] = (mask(8) << 4) | (mask(16) << 16);
regVal[MISCREG_DR7] = 1 << 10;
+
+LocalApicBase lApicBase = 0;
+lApicBase.base = 0xFEE0 >> 12;
+lApicBase.enable = 1;
+// The "bsp" bit will be set when this register is read, since then
we'll
+// have a ThreadContext to check the contextId from.
+regVal[MISCREG_APIC_BASE] = lApicBase;
}
ISA::ISA(Params *p)
@@ -148,6 +168,12 @@
return insertBits(fsw, 13, 11, top);
}
+if (miscReg == MISCREG_APIC_BASE) {
+LocalApicBase base = regVal[MISCREG_APIC_BASE];
+base.bsp = (tc->contextId() == 0);
+return base;
+}
+
return readMiscRegNoEffect(miscReg);
}
diff --git a/src/arch/x86/utility.cc b/src/arch/x86/utility.cc
index b430124..13019e9 100644
--- a/src/arch/x86/utility.cc
+++ b/src/arch/x86/utility.cc
@@ -71,7 +71,8 @@
}
}
-void initCPU(ThreadContext *tc, int cpuId)
+void
+initCPU(ThreadContext *tc, int cpuId)
{
// This function is essentially performing a reset. The actual INIT
// interrupt does a subset of this, so we'll piggyback on some of its
@@ -79,109 +80,11 @@
InitInterrupt init(0);
init.invoke(tc);
-PCState pc = tc->pcState();
-pc.upc(0);
-pc.nupc(1);
-tc->pcState(pc);
-
-// These next two loops zero internal microcode and implicit registers.
-// They aren't specified by the ISA but are used internally by M5's
-// implementation.
-for (int index = 0; index < NumMicroIntRegs; index++) {
-tc->setIntReg(INTREG_MICRO(index), 0);
-}
-
-for (int index = 0; index < NumImplicitIntRegs; index++) {
-tc->setIntReg(INTREG_IMPLICIT(index), 0);
-}
-
// Set integer register EAX to 0 to indicate that the optional BIST
// passed. No BIST actually runs, but software may still check this
// register for errors.
tc->setIntReg(INTREG_RAX, 0);
-tc->setMiscReg(MISCREG_CR0, 0x6010ULL);
-tc->setMiscReg(MISCREG_CR8, 0);
-
-// TODO initialize x87, 64 bit, and 128 bit media state
-
-tc->setMiscReg(MISCREG_MTRRCAP, 0x0508);
-for (int i = 0; i < 8; i++) {
-tc->setMiscReg(MISCREG_MTRR_PHYS_BASE(i), 0);
-tc->setMiscReg(MISCREG_MTRR_PHYS_MASK(i), 0);
-}
-tc->setMiscReg(MISCREG_MTRR_FIX_64K_0, 0);
-tc->setMiscReg(MISCREG_MTRR_FIX_16K_8, 0);
-tc->setMiscReg(MISCREG_MTRR_FIX_16K_A, 0);
-tc->setMiscReg(MISCREG_MTRR_FIX_4K_C, 0);
-tc->setMiscReg(MISCREG_MTRR_FIX_4K_C8000, 0);
-tc->setMiscReg(MISCREG_MTRR_FIX_4K_D, 0);
-tc->setMiscReg(MISCREG_MTRR_FIX_4K_D8000, 0);
-tc->setMiscReg(MISCREG_MTRR_FIX_4K_E, 0);
-tc->setMiscReg(MISCREG_MTRR_FIX_4K_E8000, 0);
-tc->setMiscReg(MISCREG_MTRR_FIX_4K_F, 0);
-tc->setMiscReg(MISCREG_MTRR_FIX_4K_F8000, 0);
-
-tc->setMiscReg(MISCREG_DEF_TYPE, 0);
-
-tc->setMiscReg(MISCREG_MCG_CAP, 0x104);
-tc->setMiscReg(MISCREG_MCG_STATUS, 0);
-tc->setMiscReg(MISCREG_MCG_CTL, 0);
-
-for (int i = 0; i < 5; i++) {
-tc->setMiscReg(MISCREG_MC_CTL(i), 0);
-tc->setMiscReg(MISCREG_MC_STATUS(i), 0);
-tc->setMiscReg(MISCREG_MC_ADDR(i), 0);
-tc->setMiscReg(MISCREG_MC_MISC(i), 0);
-}
-
-tc->setMiscReg(MISCREG_TSC, 0);
-tc->setMiscReg(MISCREG_TSC_AUX, 0);
-
-for (int i = 0; i < 4; i++) {
-tc->setMiscReg(MISCREG_PERF_EVT_SEL(i), 0);
-tc->setMiscReg(MISCREG_PERF_EVT_CTR(i), 0);
-}
-
-tc->setMiscReg(MISCREG_STAR, 0);
-tc->setMiscReg(MISCREG_LSTAR, 0);
-tc->setMiscReg(MISCREG_CSTAR, 0);
-
-tc->setMiscReg(MISCREG_SF_MASK, 0);
