[gem5-dev] Change in public/gem5[master]: arch-arm: Change function name for banked miscregs

2018-02-07 Thread Giacomo Travaglini (Gerrit) 
Giacomo Travaglini has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/7982 )


Change subject: arch-arm: Change function name for banked miscregs
..

arch-arm: Change function name for banked miscregs

This commit changes the function's name used for retrieving the index of a
security banked register given the flatten index. This will avoid confusion
with flattenRegId, which has a different purpose.

Change-Id: I470ffb55916cb7fc9f78e071a7f2e609c1829f1a
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Nikos Nikoleris 
Reviewed-on: https://gem5-review.googlesource.com/7982
Maintainer: Andreas Sandberg 
---
M src/arch/arm/insts/static_inst.cc
M src/arch/arm/isa/insts/misc.isa
M src/arch/arm/isa/operands.isa
M src/arch/arm/miscregs.cc
M src/arch/arm/miscregs.hh
M src/arch/arm/table_walker.cc
M src/arch/arm/tlb.cc
7 files changed, 31 insertions(+), 31 deletions(-)

Approvals:
  Nikos Nikoleris: Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved



diff --git a/src/arch/arm/insts/static_inst.cc  
b/src/arch/arm/insts/static_inst.cc

index f7a9745..aace1de 100644
--- a/src/arch/arm/insts/static_inst.cc
+++ b/src/arch/arm/insts/static_inst.cc
@@ -880,7 +880,7 @@

 // Get the index of the banked version of SCTLR:
 // SCTLR_s or SCTLR_ns.
-auto banked_sctlr = flattenMiscRegNsBanked(
+auto banked_sctlr = snsBankedIndex(
 MISCREG_SCTLR, tc, !inSecureState(tc));

 // SCTLR.SED bit is enabling/disabling the ue of SETEND  
instruction.
diff --git a/src/arch/arm/isa/insts/misc.isa  
b/src/arch/arm/isa/insts/misc.isa

index 23962b0..8745e86 100644
--- a/src/arch/arm/isa/insts/misc.isa
+++ b/src/arch/arm/isa/insts/misc.isa
@@ -872,7 +872,7 @@
 exec_output += PredOpExecute.subst(mcr14Iop)

 mrc15code = '''
-int preFlatOp1 = flattenMiscRegNsBanked(op1, xc->tcBase());
+int preFlatOp1 = snsBankedIndex(op1, xc->tcBase());
 MiscRegIndex miscReg = (MiscRegIndex)
xc->tcBase()->flattenRegId(RegId(MiscRegClass,
   preFlatOp1)).index();
@@ -904,7 +904,7 @@


 mcr15code = '''
-int preFlatDest = flattenMiscRegNsBanked(dest, xc->tcBase());
+int preFlatDest = snsBankedIndex(dest, xc->tcBase());
 MiscRegIndex miscReg = (MiscRegIndex)
xc->tcBase()->flattenRegId(RegId(MiscRegClass,
   preFlatDest)).index();
@@ -937,7 +937,7 @@


 mrrc15code = '''
-int preFlatOp1 = flattenMiscRegNsBanked(op1, xc->tcBase());
+int preFlatOp1 = snsBankedIndex(op1, xc->tcBase());
 MiscRegIndex miscReg = (MiscRegIndex)
xc->tcBase()->flattenRegId(RegId(MiscRegClass,
   preFlatOp1)).index();
@@ -968,7 +968,7 @@


 mcrr15code = '''
-int preFlatDest = flattenMiscRegNsBanked(dest, xc->tcBase());
+int preFlatDest = snsBankedIndex(dest, xc->tcBase());
 MiscRegIndex miscReg = (MiscRegIndex)
xc->tcBase()->flattenRegId(RegId(MiscRegClass,

preFlatDest)).index();

@@ -1045,7 +1045,7 @@
 exec_output += PredOpExecute.subst(clrexIop)

 McrDcCheckCode = '''
-int preFlatDest = flattenMiscRegNsBanked(dest, xc->tcBase());
+int preFlatDest = snsBankedIndex(dest, xc->tcBase());
 MiscRegIndex miscReg = (MiscRegIndex) xc->tcBase()->flattenRegId(
 RegId(MiscRegClass, preFlatDest)).index();
 bool hypTrap  = mcrMrc15TrapToHyp(miscReg, Hcr, Cpsr, Scr, Hdcr,  
Hstr,

diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa
index babf0ac..3daba57 100644
--- a/src/arch/arm/isa/operands.isa
+++ b/src/arch/arm/isa/operands.isa
@@ -102,11 +102,11 @@
 xc->%(func)s(this, %(op_idx)s, (%(final_val)s) & mask(32))
 '''
 cntrlNsBankedWrite = '''
-xc->setMiscReg(flattenMiscRegNsBanked(dest,  
xc->tcBase()), %(final_val)s)

+xc->setMiscReg(snsBankedIndex(dest, xc->tcBase()), %(final_val)s)
 '''

 cntrlNsBankedRead = '''
-xc->readMiscReg(flattenMiscRegNsBanked(op1, xc->tcBase()))
+xc->readMiscReg(snsBankedIndex(op1, xc->tcBase()))
 '''

 #PCState operands need to have a sorting index (the number at the end)
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index 445ba18..a9031fe 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -815,14 +815,14 @@
 }

 int
-flattenMiscRegNsBanked(MiscRegIndex reg, ThreadContext *tc)
+snsBankedIndex(MiscRegIndex reg, ThreadContext *tc)
 {
 SCR scr = tc->readMiscReg(MISCREG_SCR);
-return flattenMiscRegNsBanked(reg, tc, scr.ns);
+return snsBankedIndex(reg, tc,

[gem5-dev] Change in public/gem5[master]: arch-arm: Change function name for banked miscregs

2018-02-07 Thread Giacomo Travaglini (Gerrit) 

Hello Nikos Nikoleris, Andreas Sandberg,

I'd like you to reexamine a change. Please visit

https://gem5-review.googlesource.com/7982

to look at the new patch set (#2).

Change subject: arch-arm: Change function name for banked miscregs
..

arch-arm: Change function name for banked miscregs

This commit changes the function's name used for retrieving the index of a
security banked register given the flatten index. This will avoid confusion
with flattenRegId, which has a different purpose.

Change-Id: I470ffb55916cb7fc9f78e071a7f2e609c1829f1a
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Nikos Nikoleris 
---
M src/arch/arm/insts/static_inst.cc
M src/arch/arm/isa/insts/misc.isa
M src/arch/arm/isa/operands.isa
M src/arch/arm/miscregs.cc
M src/arch/arm/miscregs.hh
M src/arch/arm/table_walker.cc
M src/arch/arm/tlb.cc
7 files changed, 31 insertions(+), 31 deletions(-)


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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I470ffb55916cb7fc9f78e071a7f2e609c1829f1a
Gerrit-Change-Number: 7982
Gerrit-PatchSet: 2
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Nikos Nikoleris 
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[gem5-dev] Change in public/gem5[master]: arch-arm: Change function name for banked miscregs

2018-02-07 Thread Giacomo Travaglini (Gerrit) 

Hello Nikos Nikoleris,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/7982

to review the following change.


Change subject: arch-arm: Change function name for banked miscregs
..

arch-arm: Change function name for banked miscregs

This commit changes the function's name used for retrieving the index of a
security banked register given the flatten index. This will avoid confusion
with flattenRegId, which has a different purpose.

Change-Id: I470ffb55916cb7fc9f78e071a7f2e609c1829f1a
Signed-off-by: Giacomo Travaglini 
Reviewed-by: Nikos Nikoleris 
---
M src/arch/arm/insts/static_inst.cc
M src/arch/arm/isa/insts/misc.isa
M src/arch/arm/isa/operands.isa
M src/arch/arm/miscregs.cc
M src/arch/arm/miscregs.hh
M src/arch/arm/table_walker.cc
M src/arch/arm/tlb.cc
7 files changed, 30 insertions(+), 30 deletions(-)



diff --git a/src/arch/arm/insts/static_inst.cc  
b/src/arch/arm/insts/static_inst.cc

index 106ec32..b5cf58f 100644
--- a/src/arch/arm/insts/static_inst.cc
+++ b/src/arch/arm/insts/static_inst.cc
@@ -880,7 +880,7 @@

 // Get the index of the banked version of SCTLR:
 // SCTLR_s or SCTLR_ns.
-auto banked_sctlr = flattenMiscRegNsBanked(
+auto banked_sctlr = snsBankedIndex(
 MISCREG_SCTLR, tc, !inSecureState(tc));

 // SCTLR.SED bit is enabling/disabling the ue of SETEND  
instruction.
diff --git a/src/arch/arm/isa/insts/misc.isa  
b/src/arch/arm/isa/insts/misc.isa

index 23962b0..13da2bf 100644
--- a/src/arch/arm/isa/insts/misc.isa
+++ b/src/arch/arm/isa/insts/misc.isa
@@ -872,7 +872,7 @@
 exec_output += PredOpExecute.subst(mcr14Iop)

 mrc15code = '''
-int preFlatOp1 = flattenMiscRegNsBanked(op1, xc->tcBase());
+int preFlatOp1 = snsBankedIndex(op1, xc->tcBase());
 MiscRegIndex miscReg = (MiscRegIndex)
xc->tcBase()->flattenRegId(RegId(MiscRegClass,
   preFlatOp1)).index();
@@ -904,7 +904,7 @@


 mcr15code = '''
-int preFlatDest = flattenMiscRegNsBanked(dest, xc->tcBase());
+int preFlatDest = snsBankedIndex(dest, xc->tcBase());
 MiscRegIndex miscReg = (MiscRegIndex)
xc->tcBase()->flattenRegId(RegId(MiscRegClass,
   preFlatDest)).index();
@@ -937,7 +937,7 @@


 mrrc15code = '''
-int preFlatOp1 = flattenMiscRegNsBanked(op1, xc->tcBase());
+int preFlatOp1 = snsBankedIndex(op1, xc->tcBase());
 MiscRegIndex miscReg = (MiscRegIndex)
xc->tcBase()->flattenRegId(RegId(MiscRegClass,
   preFlatOp1)).index();
@@ -968,7 +968,7 @@


 mcrr15code = '''
-int preFlatDest = flattenMiscRegNsBanked(dest, xc->tcBase());
+int preFlatDest = snsBankedIndex(dest, xc->tcBase());
 MiscRegIndex miscReg = (MiscRegIndex)
xc->tcBase()->flattenRegId(RegId(MiscRegClass,

preFlatDest)).index();

diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa
index babf0ac..3daba57 100644
--- a/src/arch/arm/isa/operands.isa
+++ b/src/arch/arm/isa/operands.isa
@@ -102,11 +102,11 @@
 xc->%(func)s(this, %(op_idx)s, (%(final_val)s) & mask(32))
 '''
 cntrlNsBankedWrite = '''
-xc->setMiscReg(flattenMiscRegNsBanked(dest,  
xc->tcBase()), %(final_val)s)

+xc->setMiscReg(snsBankedIndex(dest, xc->tcBase()), %(final_val)s)
 '''

 cntrlNsBankedRead = '''
-xc->readMiscReg(flattenMiscRegNsBanked(op1, xc->tcBase()))
+xc->readMiscReg(snsBankedIndex(op1, xc->tcBase()))
 '''

 #PCState operands need to have a sorting index (the number at the end)
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index 445ba18..a9031fe 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -815,14 +815,14 @@
 }

 int
-flattenMiscRegNsBanked(MiscRegIndex reg, ThreadContext *tc)
+snsBankedIndex(MiscRegIndex reg, ThreadContext *tc)
 {
 SCR scr = tc->readMiscReg(MISCREG_SCR);
-return flattenMiscRegNsBanked(reg, tc, scr.ns);
+return snsBankedIndex(reg, tc, scr.ns);
 }

 int
-flattenMiscRegNsBanked(MiscRegIndex reg, ThreadContext *tc, bool ns)
+snsBankedIndex(MiscRegIndex reg, ThreadContext *tc, bool ns)
 {
 int reg_as_int = static_cast(reg);
 if (miscRegInfo[reg][MISCREG_BANKED]) {
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index 779ead7..8cfa013 100644
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -1891,14 +1891,14 @@
 // Uses just the scr.ns bit to pre flatten the misc regs. This is  
useful

 // for MCR/MRC instructions
 int
-flattenMiscRegNsBanked(MiscRegIndex reg, ThreadContext *tc);
+