[gem5-dev] Change in public/gem5[master]: arch-riscv: Correct syscall argument reg count

[Alec Roelke (Gerrit)]

Alec Roelke has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/7081 )


Change subject: arch-riscv: Correct syscall argument reg count
..

arch-riscv: Correct syscall argument reg count

As per the discussion in patch #6904 and the Linux 4.15 kernel code for
RISC-V, RISC-V has 7 system call argument registers, x10 through x16 (a0
through a6), with x17 (a7) being used for the system call number.

Change-Id: I0080eca78ffa844b322bb2cff2a51ab2815f3809
Reviewed-on: https://gem5-review.googlesource.com/7081
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Tuan Ta 
Maintainer: Alec Roelke 
---
M src/arch/riscv/registers.hh
1 file changed, 4 insertions(+), 4 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, but someone else must approve
  Tuan Ta: Looks good to me, approved
  Alec Roelke: Looks good to me, approved



diff --git a/src/arch/riscv/registers.hh b/src/arch/riscv/registers.hh
index 01e3859..a61554c 100644
--- a/src/arch/riscv/registers.hh
+++ b/src/arch/riscv/registers.hh
@@ -97,6 +97,10 @@
 const std::vector ArgumentRegs = {10, 11, 12, 13, 14, 15, 16, 17};
 const int AMOTempReg = 32;

+const int SyscallPseudoReturnReg = 10;
+const std::vector SyscallArgumentRegs = {10, 11, 12, 13, 14, 15, 16};
+const int SyscallNumReg = 17;
+
 const std::vector IntRegNames = {
 "zero", "ra", "sp", "gp",
 "tp", "t0", "t1", "t2",
@@ -118,10 +122,6 @@
 "ft8", "ft9", "ft10", "ft11"
 };

-const int SyscallNumReg = 17;
-const std::vector SyscallArgumentRegs = {10, 11, 12, 13};
-const int SyscallPseudoReturnReg = 10;
-
 enum MiscRegIndex {
 MISCREG_USTATUS = 0x000,
 MISCREG_UIE = 0x004,

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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: I0080eca78ffa844b322bb2cff2a51ab2815f3809
Gerrit-Change-Number: 7081
Gerrit-PatchSet: 2
Gerrit-Owner: Alec Roelke 
Gerrit-Reviewer: Alec Roelke 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: Tuan Ta 
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[gem5-dev] Change in public/gem5[master]: arch-riscv: Correct syscall argument reg count

[Alec Roelke (Gerrit)]

Alec Roelke has uploaded this change for review. (  
https://gem5-review.googlesource.com/7081



Change subject: arch-riscv: Correct syscall argument reg count
..

arch-riscv: Correct syscall argument reg count

As per the discussion in patch #6904 and the Linux 4.15 kernel code for
RISC-V, RISC-V has 7 system call argument registers, x10 through x16 (a0
through a6), with x17 (a7) being used for the system call number.

Change-Id: I0080eca78ffa844b322bb2cff2a51ab2815f3809
---
M src/arch/riscv/registers.hh
1 file changed, 4 insertions(+), 4 deletions(-)



diff --git a/src/arch/riscv/registers.hh b/src/arch/riscv/registers.hh
index 01e3859..a61554c 100644
--- a/src/arch/riscv/registers.hh
+++ b/src/arch/riscv/registers.hh
@@ -97,6 +97,10 @@
 const std::vector ArgumentRegs = {10, 11, 12, 13, 14, 15, 16, 17};
 const int AMOTempReg = 32;

+const int SyscallPseudoReturnReg = 10;
+const std::vector SyscallArgumentRegs = {10, 11, 12, 13, 14, 15, 16};
+const int SyscallNumReg = 17;
+
 const std::vector IntRegNames = {
 "zero", "ra", "sp", "gp",
 "tp", "t0", "t1", "t2",
@@ -118,10 +122,6 @@
 "ft8", "ft9", "ft10", "ft11"
 };

-const int SyscallNumReg = 17;
-const std::vector SyscallArgumentRegs = {10, 11, 12, 13};
-const int SyscallPseudoReturnReg = 10;
-
 enum MiscRegIndex {
 MISCREG_USTATUS = 0x000,
 MISCREG_UIE = 0x004,

--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I0080eca78ffa844b322bb2cff2a51ab2815f3809
Gerrit-Change-Number: 7081
Gerrit-PatchSet: 1
Gerrit-Owner: Alec Roelke 
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