[gem5-dev] Change in public/gem5[master]: cpu: Result refactoring

2017-07-05 Thread Andreas Sandberg (Gerrit) 
Andreas Sandberg has submitted this change and it was merged. (  
https://gem5-review.googlesource.com/2703 )


Change subject: cpu: Result refactoring
..

cpu: Result refactoring

The Result union used to collect the result of an instruction is now a
class of its own, with its constructor, and explicit casting methods for
cleanliness.

This is also a stepping stone to have vector registers, and instructions
that produce a vector register as output.

Change-Id: I6f40c11cb5e835d8b11f7804a4e967aff18025b9
Reviewed-by: Andreas Sandberg 
Reviewed-on: https://gem5-review.googlesource.com/2703
Reviewed-by: Anthony Gutierrez 
Reviewed-by: Jason Lowe-Power 
Maintainer: Andreas Sandberg 
---
M src/cpu/base_dyn_inst.hh
M src/cpu/checker/cpu.hh
M src/cpu/checker/cpu_impl.hh
A src/cpu/inst_res.hh
4 files changed, 205 insertions(+), 78 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  Anthony Gutierrez: Looks good to me, approved



diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index 9c69523..a8e619c 100644
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011,2013 ARM Limited
+ * Copyright (c) 2011,2013,2016 ARM Limited
  * Copyright (c) 2013 Advanced Micro Devices, Inc.
  * All rights reserved.
  *
@@ -49,18 +49,19 @@
 #include 
 #include 
 #include 
-#include 
 #include 
+#include 

 #include "arch/generic/tlb.hh"
 #include "arch/utility.hh"
 #include "base/trace.hh"
 #include "config/the_isa.hh"
 #include "cpu/checker/cpu.hh"
-#include "cpu/o3/comm.hh"
 #include "cpu/exec_context.hh"
 #include "cpu/exetrace.hh"
+#include "cpu/inst_res.hh"
 #include "cpu/inst_seq.hh"
+#include "cpu/o3/comm.hh"
 #include "cpu/op_class.hh"
 #include "cpu/static_inst.hh"
 #include "cpu/translation.hh"
@@ -94,15 +95,6 @@
 MaxInstDestRegs = TheISA::MaxInstDestRegs   /// Max dest regs
 };

-union Result {
-uint64_t integer;
-double dbl;
-void set(uint64_t i) { integer = i; }
-void set(double d) { dbl = d; }
-void get(uint64_t& i) { i = integer; }
-void get(double& d) { d = dbl; }
-};
-
   protected:
 enum Status {
 IqEntry, /// Instruction is in the IQ
@@ -174,7 +166,7 @@
 /** The result of the instruction; assumes an instruction can have many
  *  destination registers.
  */
-std::queue instResult;
+std::queue instResult;

 /** PC state for this instruction. */
 TheISA::PCState pc;
@@ -606,56 +598,55 @@
 /** Returns the logical register index of the i'th source register. */
 const RegId& srcRegIdx(int i) const { return staticInst->srcRegIdx(i);  
}


-/** Pops a result off the instResult queue */
-template 
-void popResult(T& t)
+/** Return the size of the instResult queue. */
+uint8_t resultSize() { return instResult.size(); }
+
+/** Pops a result off the instResult queue.
+ * If the result stack is empty, return the default value.
+ * */
+InstResult popResult(InstResult dflt = InstResult())
 {
 if (!instResult.empty()) {
-instResult.front().get(t);
+InstResult t = instResult.front();
 instResult.pop();
+return t;
 }
+return dflt;
 }

-/** Read the most recent result stored by this instruction */
-template 
-void readResult(T& t)
-{
-instResult.back().get(t);
-}
-
-/** Pushes a result onto the instResult queue */
-template 
-void setResult(T t)
+/** Pushes a result onto the instResult queue. */
+template
+void setScalarResult(T&& t)
 {
 if (instFlags[RecordResult]) {
-Result instRes;
-instRes.set(t);
-instResult.push(instRes);
+instResult.push(InstResult(std::forward(t),
+InstResult::ResultType::Scalar));
 }
 }

 /** Records an integer register being set to a value. */
 void setIntRegOperand(const StaticInst *si, int idx, IntReg val)
 {
-setResult(val);
+setScalarResult(val);
 }

 /** Records a CC register being set to a value. */
 void setCCRegOperand(const StaticInst *si, int idx, CCReg val)
 {
-setResult(val);
+setScalarResult(val);
 }

 /** Records an fp register being set to a value. */
 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
 {
-setResult(val);
+setScalarResult(val);
 }

 /** Records an fp register being set to an integer value. */
-void setFloatRegOperandBits(const StaticInst *si, int idx,  
FloatRegBits val)

+void
+setFloatRegOperandBits(const StaticInst *si, int

[gem5-dev] Change in public/gem5[master]: cpu: Result refactoring

2017-04-05 Thread Curtis Dunham (Gerrit) 

Hello Andreas Sandberg,

I'd like you to do a code review. Please visit

https://gem5-review.googlesource.com/2703

to review the following change.


Change subject: cpu: Result refactoring
..

cpu: Result refactoring

The Result union used to collect the result of an instruction is now a
class of its own, with its constructor, and explicit casting methods for
cleanliness.

This is also a stepping stone to have vector registers, and instructions
that produce a vector register as output.

Change-Id: I6f40c11cb5e835d8b11f7804a4e967aff18025b9
Reviewed-by: Andreas Sandberg 
---
M src/cpu/base_dyn_inst.hh
M src/cpu/checker/cpu.hh
M src/cpu/checker/cpu_impl.hh
A src/cpu/inst_res.hh
4 files changed, 205 insertions(+), 78 deletions(-)



diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index 9c69523..a8e619c 100644
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011,2013 ARM Limited
+ * Copyright (c) 2011,2013,2016 ARM Limited
  * Copyright (c) 2013 Advanced Micro Devices, Inc.
  * All rights reserved.
  *
@@ -49,18 +49,19 @@
 #include 
 #include 
 #include 
-#include 
 #include 
+#include 

 #include "arch/generic/tlb.hh"
 #include "arch/utility.hh"
 #include "base/trace.hh"
 #include "config/the_isa.hh"
 #include "cpu/checker/cpu.hh"
-#include "cpu/o3/comm.hh"
 #include "cpu/exec_context.hh"
 #include "cpu/exetrace.hh"
+#include "cpu/inst_res.hh"
 #include "cpu/inst_seq.hh"
+#include "cpu/o3/comm.hh"
 #include "cpu/op_class.hh"
 #include "cpu/static_inst.hh"
 #include "cpu/translation.hh"
@@ -92,15 +93,6 @@
 enum {
 MaxInstSrcRegs = TheISA::MaxInstSrcRegs,/// Max source regs
 MaxInstDestRegs = TheISA::MaxInstDestRegs   /// Max dest regs
-};
-
-union Result {
-uint64_t integer;
-double dbl;
-void set(uint64_t i) { integer = i; }
-void set(double d) { dbl = d; }
-void get(uint64_t& i) { i = integer; }
-void get(double& d) { d = dbl; }
 };

   protected:
@@ -174,7 +166,7 @@
 /** The result of the instruction; assumes an instruction can have many
  *  destination registers.
  */
-std::queue instResult;
+std::queue instResult;

 /** PC state for this instruction. */
 TheISA::PCState pc;
@@ -606,56 +598,55 @@
 /** Returns the logical register index of the i'th source register. */
 const RegId& srcRegIdx(int i) const { return staticInst->srcRegIdx(i);  
}


-/** Pops a result off the instResult queue */
-template 
-void popResult(T& t)
+/** Return the size of the instResult queue. */
+uint8_t resultSize() { return instResult.size(); }
+
+/** Pops a result off the instResult queue.
+ * If the result stack is empty, return the default value.
+ * */
+InstResult popResult(InstResult dflt = InstResult())
 {
 if (!instResult.empty()) {
-instResult.front().get(t);
+InstResult t = instResult.front();
 instResult.pop();
+return t;
 }
+return dflt;
 }

-/** Read the most recent result stored by this instruction */
-template 
-void readResult(T& t)
-{
-instResult.back().get(t);
-}
-
-/** Pushes a result onto the instResult queue */
-template 
-void setResult(T t)
+/** Pushes a result onto the instResult queue. */
+template
+void setScalarResult(T&& t)
 {
 if (instFlags[RecordResult]) {
-Result instRes;
-instRes.set(t);
-instResult.push(instRes);
+instResult.push(InstResult(std::forward(t),
+InstResult::ResultType::Scalar));
 }
 }

 /** Records an integer register being set to a value. */
 void setIntRegOperand(const StaticInst *si, int idx, IntReg val)
 {
-setResult(val);
+setScalarResult(val);
 }

 /** Records a CC register being set to a value. */
 void setCCRegOperand(const StaticInst *si, int idx, CCReg val)
 {
-setResult(val);
+setScalarResult(val);
 }

 /** Records an fp register being set to a value. */
 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
 {
-setResult(val);
+setScalarResult(val);
 }

 /** Records an fp register being set to an integer value. */
-void setFloatRegOperandBits(const StaticInst *si, int idx,  
FloatRegBits val)

+void
+setFloatRegOperandBits(const StaticInst *si, int idx, FloatRegBits val)
 {
-setResult(val);
+setScalarResult(val);
 }

 /** Records that one of the source registers is ready. */
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 304caaa..6571d03 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011 ARM