Re: [gem5-dev] Review Request 3835: sim: expand AuxVector class
--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/3835/ --- (Updated Feb. 24, 2017, 6:59 p.m.) Review request for Default. Repository: gem5 Description (updated) --- Changeset 11891:11b2a627263e --- sim: expand AuxVector class The AuxVector class is responsible for holding Process data (in SE Mode of course). The data that it holds is normally setup by an OS kernel in the process address space. The purpose behind doing this is to pass in information that the process will need for various reasons. (Check out the enum in the header file for an idea of what the AuxVector holds.) The AuxVector struct was changed into a class and encapsulation methods were added to protect access to the member variables. The host ISA may have a different endianness than the simulated ISA. Since data is passed between the process address space and the simulator for auxiliary vectors, we need to worry about maintaining endianness for the right context. Diffs (updated) - src/arch/riscv/process.cc 5ea85692a53ea437c95e5a199884bd3a5266f820 src/arch/sparc/process.cc 5ea85692a53ea437c95e5a199884bd3a5266f820 src/arch/x86/process.cc 5ea85692a53ea437c95e5a199884bd3a5266f820 src/sim/aux_vector.hh 5ea85692a53ea437c95e5a199884bd3a5266f820 src/sim/aux_vector.cc 5ea85692a53ea437c95e5a199884bd3a5266f820 src/arch/alpha/process.cc 5ea85692a53ea437c95e5a199884bd3a5266f820 src/arch/arm/process.cc 5ea85692a53ea437c95e5a199884bd3a5266f820 src/arch/mips/process.cc 5ea85692a53ea437c95e5a199884bd3a5266f820 src/arch/power/process.cc 5ea85692a53ea437c95e5a199884bd3a5266f820 Diff: http://reviews.gem5.org/r/3835/diff/ Testing --- Thanks, Brandon Potter ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
Re: [gem5-dev] Review Request 3835: sim: expand AuxVector class
--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/3835/#review9475 --- Ship it! Ship It! - Michael LeBeane On Feb. 24, 2017, 5:23 a.m., Brandon Potter wrote: > > --- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/3835/ > --- > > (Updated Feb. 24, 2017, 5:23 a.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > --- > > Changeset 11891:da5745659ea2 > --- > sim: expand AuxVector class > > The AuxVector class is responsible for holding Process data (in SE Mode > of course). The data that it holds is normally setup by an OS kernel in > the process address space. The purpose behind doing this is to pass in > information that the process will need for various reasons. (Check out > the enum in the header file for an idea of what the AuxVector holds.) > > The AuxVector struct was changed into a class and encapsulation methods > were added to protect access to the member variables. > > The host ISA may have a different endianness than the simulated ISA. > Since data is passed between the process address space and the > simulator for auxiliary vectors, we need to worry about maintaining > endianness for the right context. > > > Diffs > - > > src/arch/alpha/process.cc 5ea85692a53ea437c95e5a199884bd3a5266f820 > src/sim/aux_vector.hh 5ea85692a53ea437c95e5a199884bd3a5266f820 > src/sim/aux_vector.cc 5ea85692a53ea437c95e5a199884bd3a5266f820 > src/arch/sparc/process.cc 5ea85692a53ea437c95e5a199884bd3a5266f820 > src/arch/x86/process.cc 5ea85692a53ea437c95e5a199884bd3a5266f820 > src/arch/power/process.cc 5ea85692a53ea437c95e5a199884bd3a5266f820 > src/arch/riscv/process.cc 5ea85692a53ea437c95e5a199884bd3a5266f820 > src/arch/arm/process.cc 5ea85692a53ea437c95e5a199884bd3a5266f820 > src/arch/mips/process.cc 5ea85692a53ea437c95e5a199884bd3a5266f820 > > Diff: http://reviews.gem5.org/r/3835/diff/ > > > Testing > --- > > > Thanks, > > Brandon Potter > > ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
Re: [gem5-dev] Review Request 3835: sim: expand AuxVector class
--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/3835/ --- (Updated Feb. 24, 2017, 5:23 a.m.) Review request for Default. Repository: gem5 Description (updated) --- Changeset 11891:da5745659ea2 --- sim: expand AuxVector class The AuxVector class is responsible for holding Process data (in SE Mode of course). The data that it holds is normally setup by an OS kernel in the process address space. The purpose behind doing this is to pass in information that the process will need for various reasons. (Check out the enum in the header file for an idea of what the AuxVector holds.) The AuxVector struct was changed into a class and encapsulation methods were added to protect access to the member variables. The host ISA may have a different endianness than the simulated ISA. Since data is passed between the process address space and the simulator for auxiliary vectors, we need to worry about maintaining endianness for the right context. Diffs (updated) - src/arch/alpha/process.cc 5ea85692a53ea437c95e5a199884bd3a5266f820 src/sim/aux_vector.hh 5ea85692a53ea437c95e5a199884bd3a5266f820 src/sim/aux_vector.cc 5ea85692a53ea437c95e5a199884bd3a5266f820 src/arch/sparc/process.cc 5ea85692a53ea437c95e5a199884bd3a5266f820 src/arch/x86/process.cc 5ea85692a53ea437c95e5a199884bd3a5266f820 src/arch/power/process.cc 5ea85692a53ea437c95e5a199884bd3a5266f820 src/arch/riscv/process.cc 5ea85692a53ea437c95e5a199884bd3a5266f820 src/arch/arm/process.cc 5ea85692a53ea437c95e5a199884bd3a5266f820 src/arch/mips/process.cc 5ea85692a53ea437c95e5a199884bd3a5266f820 Diff: http://reviews.gem5.org/r/3835/diff/ Testing --- Thanks, Brandon Potter ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
[gem5-dev] Review Request 3835: sim: expand AuxVector class
--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/3835/ --- Review request for Default. Repository: gem5 Description --- Changeset 11891:f2f68a484d6b --- sim: expand AuxVector class The AuxVector class is responsible for holding Process data (in SE Mode of course). The data that it holds is normally setup by an OS kernel in the process address space. The purpose behind doing this is to pass in information that the process will need for various reasons. (Check out the enum in the header file for an idea of what the AuxVector holds.) The AuxVector struct was changed into a class and encapsulation methods were added to protect access to the member variables. The host ISA may have a different endianness than the simulated ISA. Since data is passed between the process address space and the simulator for auxiliary vectors, we need to worry about maintaining endianness for the right context. The default storage choice for the auxiliary vectors is to maintain the guest endianness in the class members and convert out to the host endianness with the getHost* accessors. Diffs - src/sim/aux_vector.cc 5ea85692a53ea437c95e5a199884bd3a5266f820 src/arch/arm/process.cc 5ea85692a53ea437c95e5a199884bd3a5266f820 src/arch/mips/process.cc 5ea85692a53ea437c95e5a199884bd3a5266f820 src/arch/power/process.cc 5ea85692a53ea437c95e5a199884bd3a5266f820 src/arch/riscv/process.cc 5ea85692a53ea437c95e5a199884bd3a5266f820 src/arch/sparc/process.cc 5ea85692a53ea437c95e5a199884bd3a5266f820 src/arch/x86/process.cc 5ea85692a53ea437c95e5a199884bd3a5266f820 src/sim/aux_vector.hh 5ea85692a53ea437c95e5a199884bd3a5266f820 src/arch/alpha/process.cc 5ea85692a53ea437c95e5a199884bd3a5266f820 Diff: http://reviews.gem5.org/r/3835/diff/ Testing --- Thanks, Brandon Potter ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
