Re: [gem5-dev] Review Request 2322: SegInit, x86: Segment initialization to support KvmCPU in SE
--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2322/#review5336 --- Ship it! Ship It! - Andreas Sandberg On Sept. 16, 2014, 4:37 p.m., Alexandru Dutu wrote: --- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2322/ --- (Updated Sept. 16, 2014, 4:37 p.m.) Review request for Default. Repository: gem5 Description --- Changeset 10302:8bbfa3e4752c --- SegInit, x86: Segment initialization to support KvmCPU in SE This patch sets up low and high privilege code and data segments and places them in the following order: cs low, ds low, ds, cs, in the GDT. Additionally, a syscall and page fault handler for KvmCPU in SE mode are defined. The order of the segment selectors in GDT is required in this manner for interrupt handling to work properly. Segment initialization is done for all the thread contexts. Diffs - src/arch/x86/process.cc bec0c5ffc3237096570fe4c802aeb37e1e396d1b src/arch/x86/regs/misc.hh bec0c5ffc3237096570fe4c802aeb37e1e396d1b src/arch/x86/system.hh bec0c5ffc3237096570fe4c802aeb37e1e396d1b src/arch/x86/system.cc bec0c5ffc3237096570fe4c802aeb37e1e396d1b src/sim/Process.py bec0c5ffc3237096570fe4c802aeb37e1e396d1b src/sim/process.hh bec0c5ffc3237096570fe4c802aeb37e1e396d1b src/sim/process.cc bec0c5ffc3237096570fe4c802aeb37e1e396d1b Diff: http://reviews.gem5.org/r/2322/diff/ Testing --- Quick regression tests Thanks, Alexandru Dutu ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
Re: [gem5-dev] Review Request 2322: SegInit, x86: Segment initialization to support KvmCPU in SE
On Sept. 19, 2014, 10 a.m., Andreas Sandberg wrote: Ship It! Just a minor thing: You should get rid of the SegInit keyword on the summary line since that's not in the list of recognized keywords. - Andreas --- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2322/#review5336 --- On Sept. 16, 2014, 4:37 p.m., Alexandru Dutu wrote: --- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2322/ --- (Updated Sept. 16, 2014, 4:37 p.m.) Review request for Default. Repository: gem5 Description --- Changeset 10302:8bbfa3e4752c --- SegInit, x86: Segment initialization to support KvmCPU in SE This patch sets up low and high privilege code and data segments and places them in the following order: cs low, ds low, ds, cs, in the GDT. Additionally, a syscall and page fault handler for KvmCPU in SE mode are defined. The order of the segment selectors in GDT is required in this manner for interrupt handling to work properly. Segment initialization is done for all the thread contexts. Diffs - src/arch/x86/process.cc bec0c5ffc3237096570fe4c802aeb37e1e396d1b src/arch/x86/regs/misc.hh bec0c5ffc3237096570fe4c802aeb37e1e396d1b src/arch/x86/system.hh bec0c5ffc3237096570fe4c802aeb37e1e396d1b src/arch/x86/system.cc bec0c5ffc3237096570fe4c802aeb37e1e396d1b src/sim/Process.py bec0c5ffc3237096570fe4c802aeb37e1e396d1b src/sim/process.hh bec0c5ffc3237096570fe4c802aeb37e1e396d1b src/sim/process.cc bec0c5ffc3237096570fe4c802aeb37e1e396d1b Diff: http://reviews.gem5.org/r/2322/diff/ Testing --- Quick regression tests Thanks, Alexandru Dutu ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
Re: [gem5-dev] Review Request 2322: SegInit, x86: Segment initialization to support KvmCPU in SE
--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2322/ --- (Updated Sept. 16, 2014, 3:37 p.m.) Review request for Default. Changes --- Updated syscall and page fault handler. I am reposting this mainly for people to see how changes in http://reviews.gem5.org/r/2313/ are affecting this patch. Repository: gem5 Description (updated) --- Changeset 10302:8bbfa3e4752c --- SegInit, x86: Segment initialization to support KvmCPU in SE This patch sets up low and high privilege code and data segments and places them in the following order: cs low, ds low, ds, cs, in the GDT. Additionally, a syscall and page fault handler for KvmCPU in SE mode are defined. The order of the segment selectors in GDT is required in this manner for interrupt handling to work properly. Segment initialization is done for all the thread contexts. Diffs (updated) - src/arch/x86/process.cc bec0c5ffc3237096570fe4c802aeb37e1e396d1b src/arch/x86/regs/misc.hh bec0c5ffc3237096570fe4c802aeb37e1e396d1b src/arch/x86/system.hh bec0c5ffc3237096570fe4c802aeb37e1e396d1b src/arch/x86/system.cc bec0c5ffc3237096570fe4c802aeb37e1e396d1b src/sim/Process.py bec0c5ffc3237096570fe4c802aeb37e1e396d1b src/sim/process.hh bec0c5ffc3237096570fe4c802aeb37e1e396d1b src/sim/process.cc bec0c5ffc3237096570fe4c802aeb37e1e396d1b Diff: http://reviews.gem5.org/r/2322/diff/ Testing --- Quick regression tests Thanks, Alexandru Dutu ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
Re: [gem5-dev] Review Request 2322: SegInit, x86: Segment initialization to support KvmCPU in SE
--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2322/#review5249 --- Ship it! src/sim/process.hh http://reviews.gem5.org/r/2322/#comment4791 Style issue: Member variables should not start with initial caps. Rename to kvmInSE or useKvmInSE. Looks good other than the style issue above. As far as I'm concerned, you don't need to re-post after fixing that. - Andreas Sandberg On Aug. 1, 2014, 4:53 p.m., Alexandru Dutu wrote: --- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2322/ --- (Updated Aug. 1, 2014, 4:53 p.m.) Review request for Default. Repository: gem5 Description --- Changeset 10268:53d5cfcbb5a1 --- SegInit, x86: Segment initialization to support KvmCPU in SE This patch sets up low and high privilege code and data segments and places them in the following order: cs low, ds low, ds, cs, in the GDT. Additionally, a syscall and page fault handler for KvmCPU in SE mode are defined. The order of the segment selectors in GDT is required in this manner for interrupt handling to work properly. Segment initialization is done for all the thread contexts. Diffs - src/arch/x86/process.cc c00b5ba43967e7e48a28b7ddc48c9f4afaf2ab76 src/arch/x86/regs/misc.hh c00b5ba43967e7e48a28b7ddc48c9f4afaf2ab76 src/arch/x86/system.hh c00b5ba43967e7e48a28b7ddc48c9f4afaf2ab76 src/arch/x86/system.cc c00b5ba43967e7e48a28b7ddc48c9f4afaf2ab76 src/sim/Process.py c00b5ba43967e7e48a28b7ddc48c9f4afaf2ab76 src/sim/process.hh c00b5ba43967e7e48a28b7ddc48c9f4afaf2ab76 src/sim/process.cc c00b5ba43967e7e48a28b7ddc48c9f4afaf2ab76 Diff: http://reviews.gem5.org/r/2322/diff/ Testing --- Quick regression tests Thanks, Alexandru Dutu ___ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
