Re: [gem5-dev] Review Request 2994: cpu: Change thread assignents for heterogenous SMT

2015-08-12 Thread Mitch Hayenga


 On Aug. 6, 2015, 1:56 p.m., Alexandru Dutu wrote:
  src/sim/system.hh, line 199
  http://reviews.gem5.org/r/2994/diff/1/?file=48553#file48553line199
 
  Not sure I understand why this is needed, it seems one can already 
  figure out if it is a multi-threaded system configured by checking 
  numThreads.

This is needed to determine if the system contains heterogenously-threaded 
cores (and changes how we do the thread id assignment on ARM).  Just detecting 
if a CPU has 1 thread is not sufficient if other, multi-threaded cores in the 
system may exist.


- Mitch


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On July 30, 2015, 6:46 p.m., Curtis Dunham wrote:
 
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 http://reviews.gem5.org/r/2994/
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 (Updated July 30, 2015, 6:46 p.m.)
 
 
 Review request for Default.
 
 
 Repository: gem5
 
 
 Description
 ---
 
 Trying to run an SE system with varying threads per core (SMT cores + Non-SMT
 cores) caused failures due to the CPU id assignment logic.  The comment
 about thread assignment (worrying about core 0 not having tid 0) seems
 not to be valid given that our configuration scripts initialize them in
 order.
 
 This removes that constraint so a heterogenously threaded sytem can work.
 
 
 Diffs
 -
 
   src/cpu/base.cc 40526b73c7db9ff2e03215cdfb477d024ea8d709 
   src/sim/System.py 40526b73c7db9ff2e03215cdfb477d024ea8d709 
   src/sim/system.hh 40526b73c7db9ff2e03215cdfb477d024ea8d709 
   src/sim/system.cc 40526b73c7db9ff2e03215cdfb477d024ea8d709 
 
 Diff: http://reviews.gem5.org/r/2994/diff/
 
 
 Testing
 ---
 
 
 Thanks,
 
 Curtis Dunham
 


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Re: [gem5-dev] Review Request 2994: cpu: Change thread assignents for heterogenous SMT

2015-08-06 Thread Alexandru Dutu

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src/sim/system.hh (line 199)
http://reviews.gem5.org/r/2994/#comment5956

Not sure I understand why this is needed, it seems one can already figure 
out if it is a multi-threaded system configured by checking numThreads.


- Alexandru Dutu


On July 30, 2015, 6:46 p.m., Curtis Dunham wrote:
 
 ---
 This is an automatically generated e-mail. To reply, visit:
 http://reviews.gem5.org/r/2994/
 ---
 
 (Updated July 30, 2015, 6:46 p.m.)
 
 
 Review request for Default.
 
 
 Repository: gem5
 
 
 Description
 ---
 
 Trying to run an SE system with varying threads per core (SMT cores + Non-SMT
 cores) caused failures due to the CPU id assignment logic.  The comment
 about thread assignment (worrying about core 0 not having tid 0) seems
 not to be valid given that our configuration scripts initialize them in
 order.
 
 This removes that constraint so a heterogenously threaded sytem can work.
 
 
 Diffs
 -
 
   src/cpu/base.cc 40526b73c7db9ff2e03215cdfb477d024ea8d709 
   src/sim/System.py 40526b73c7db9ff2e03215cdfb477d024ea8d709 
   src/sim/system.hh 40526b73c7db9ff2e03215cdfb477d024ea8d709 
   src/sim/system.cc 40526b73c7db9ff2e03215cdfb477d024ea8d709 
 
 Diff: http://reviews.gem5.org/r/2994/diff/
 
 
 Testing
 ---
 
 
 Thanks,
 
 Curtis Dunham
 


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