Re: [m5-dev] MIPS UTB and multiple inheritance.
OK, so the solution should probably be move the ITB/DTB functions into one base TLB and then let a unified TLB derive off of that...correct? This would allow us the two standard ITB and DTB pointers we've been using...but also avoid multiple inheritance issues as well. On Fri, Mar 6, 2009 at 2:12 AM, nathan binkert n...@binkert.org wrote: Oh, I agree there. They may both point to the same thing (unified case), but they may not. Nate Having two pointers in the CPU for the DTB and ITB is still a necessity. If you're trying to model separate structures you're going to need two of them. Ali On Mar 6, 2009, at 1:13 AM, Gabe Black wrote: I think ITBs and DTBs are usually very similar differ in a few key ways like the nx (no execute) bit in x86 for example. In x86 the DTB and ITB classes are basically just wrappers around a common TLB with one translate function, and the DTB's and ITB's version just call that with an extra parameter or two. This should generally work across other ISAs as far as I know. If the translate functions really are radically different, there isn't much overhead in having them both in there and just picking one or the other based on that parameter. I think even the generic TLB that's for SE implementations that don't have an ISA specific TLB yet just looks things up in the page table no matter what your translating. As far as whether to get rid of the separation between the ITB and DTB I think it's a good idea. I can't think of any benefit to having the separation other than that it's already there, and while it hasn't caused any other problems it prevents Korey from having a UTB implementation. We'd likely want to give it parameters which let you independently configure it's ITB and DTB (or UTB) personalities, but that should be pretty easy. This should (knock on wood) be pretty easy to implement and I'd be happy to help. Gabe nathan binkert wrote: How different are ITBs and DTBs anyway? It seems like for a UTB you'd want a single object that handles both ifetch and data translations using a common translate() method, not something that inherits from two different classes. E.g., why not just derive it from TLB? The two translation functions are different because every ISA does some different things for instructions vs data. Think about something like the executable bit. Philosophically, I agree... let's avoid virtual inheritance if at all possible. It's just not a good idea. Ok, so the question is, which of the other alternatives should we do? Gabe (mister TLB expert)? Korey (since this is mips code)? Nate ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev -- -- Korey L Sewell Graduate Student - PhD Candidate Computer Science Engineering University of Michigan ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] MIPS UTB and multiple inheritance.
Is the following correct? This is in the BaseCPU where it sets up the data and instruction TLBs it's going to use and installs defaults. I'm suspicious that this is actually installing a particular TLB to be the default in all of the CPUs, or in other words all CPUs share the same ITB and DTB. Am I crazy? dtb = Param.SparcDTB(SparcDTB(), Data TLB) itb = Param.SparcITB(SparcITB(), Instruction TLB) Gabe Gabe Black wrote: I'll keep both pointers then. I have all the non-ISA bits and X86 converted and I'm trying to test it, but I'm running into a compile error in the stats stuff. Nate? cc1plus: warnings being treated as errors build/X86_SE/base/statistics.hh: In member function 'Stats::VectorDistribution Stats::VectorDistribution::init(Stats::size_type, Stats::Counter, Stats::Counter, Stats::Counter)': build/X86_SE/base/statistics.hh:2498: warning: converting to 'Stats::size_type' from 'double' Gabe nathan binkert wrote: Oh, I agree there. They may both point to the same thing (unified case), but they may not. Nate Having two pointers in the CPU for the DTB and ITB is still a necessity. If you're trying to model separate structures you're going to need two of them. Ali On Mar 6, 2009, at 1:13 AM, Gabe Black wrote: I think ITBs and DTBs are usually very similar differ in a few key ways like the nx (no execute) bit in x86 for example. In x86 the DTB and ITB classes are basically just wrappers around a common TLB with one translate function, and the DTB's and ITB's version just call that with an extra parameter or two. This should generally work across other ISAs as far as I know. If the translate functions really are radically different, there isn't much overhead in having them both in there and just picking one or the other based on that parameter. I think even the generic TLB that's for SE implementations that don't have an ISA specific TLB yet just looks things up in the page table no matter what your translating. As far as whether to get rid of the separation between the ITB and DTB I think it's a good idea. I can't think of any benefit to having the separation other than that it's already there, and while it hasn't caused any other problems it prevents Korey from having a UTB implementation. We'd likely want to give it parameters which let you independently configure it's ITB and DTB (or UTB) personalities, but that should be pretty easy. This should (knock on wood) be pretty easy to implement and I'd be happy to help. Gabe nathan binkert wrote: How different are ITBs and DTBs anyway? It seems like for a UTB you'd want a single object that handles both ifetch and data translations using a common translate() method, not something that inherits from two different classes. E.g., why not just derive it from TLB? The two translation functions are different because every ISA does some different things for instructions vs data. Think about something like the executable bit. Philosophically, I agree... let's avoid virtual inheritance if at all possible. It's just not a good idea. Ok, so the question is, which of the other alternatives should we do? Gabe (mister TLB expert)? Korey (since this is mips code)? Nate ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] MIPS UTB and multiple inheritance.
The ITB and DTB functions should be in -the- base TLB class I hope by the end of the weekend at the latest. The UTB can then be assigned to both ITB and DTB parameters and it should work. Gabe Korey Sewell wrote: OK, so the solution should probably be move the ITB/DTB functions into one base TLB and then let a unified TLB derive off of that...correct? This would allow us the two standard ITB and DTB pointers we've been using...but also avoid multiple inheritance issues as well. On Fri, Mar 6, 2009 at 2:12 AM, nathan binkert n...@binkert.org mailto:n...@binkert.org wrote: Oh, I agree there. They may both point to the same thing (unified case), but they may not. Nate Having two pointers in the CPU for the DTB and ITB is still a necessity. If you're trying to model separate structures you're going to need two of them. Ali On Mar 6, 2009, at 1:13 AM, Gabe Black wrote: I think ITBs and DTBs are usually very similar differ in a few key ways like the nx (no execute) bit in x86 for example. In x86 the DTB and ITB classes are basically just wrappers around a common TLB with one translate function, and the DTB's and ITB's version just call that with an extra parameter or two. This should generally work across other ISAs as far as I know. If the translate functions really are radically different, there isn't much overhead in having them both in there and just picking one or the other based on that parameter. I think even the generic TLB that's for SE implementations that don't have an ISA specific TLB yet just looks things up in the page table no matter what your translating. As far as whether to get rid of the separation between the ITB and DTB I think it's a good idea. I can't think of any benefit to having the separation other than that it's already there, and while it hasn't caused any other problems it prevents Korey from having a UTB implementation. We'd likely want to give it parameters which let you independently configure it's ITB and DTB (or UTB) personalities, but that should be pretty easy. This should (knock on wood) be pretty easy to implement and I'd be happy to help. Gabe nathan binkert wrote: How different are ITBs and DTBs anyway? It seems like for a UTB you'd want a single object that handles both ifetch and data translations using a common translate() method, not something that inherits from two different classes. E.g., why not just derive it from TLB? The two translation functions are different because every ISA does some different things for instructions vs data. Think about something like the executable bit. Philosophically, I agree... let's avoid virtual inheritance if at all possible. It's just not a good idea. Ok, so the question is, which of the other alternatives should we do? Gabe (mister TLB expert)? Korey (since this is mips code)? Nate ___ m5-dev mailing list m5-dev@m5sim.org mailto:m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org mailto:m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org mailto:m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org mailto:m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev -- -- Korey L Sewell Graduate Student - PhD Candidate Computer Science Engineering University of Michigan ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] MIPS UTB and multiple inheritance.
Gabe, aren't those per-CPU python parameters? In other words, each CPU instantiates it' own set of parameters in the config file through this python interface...right? On Fri, Mar 6, 2009 at 3:09 AM, Gabe Black gbl...@eecs.umich.edu wrote: Is the following correct? This is in the BaseCPU where it sets up the data and instruction TLBs it's going to use and installs defaults. I'm suspicious that this is actually installing a particular TLB to be the default in all of the CPUs, or in other words all CPUs share the same ITB and DTB. Am I crazy? dtb = Param.SparcDTB(SparcDTB(), Data TLB) itb = Param.SparcITB(SparcITB(), Instruction TLB) Gabe Gabe Black wrote: I'll keep both pointers then. I have all the non-ISA bits and X86 converted and I'm trying to test it, but I'm running into a compile error in the stats stuff. Nate? cc1plus: warnings being treated as errors build/X86_SE/base/statistics.hh: In member function 'Stats::VectorDistribution Stats::VectorDistribution::init(Stats::size_type, Stats::Counter, Stats::Counter, Stats::Counter)': build/X86_SE/base/statistics.hh:2498: warning: converting to 'Stats::size_type' from 'double' Gabe nathan binkert wrote: Oh, I agree there. They may both point to the same thing (unified case), but they may not. Nate Having two pointers in the CPU for the DTB and ITB is still a necessity. If you're trying to model separate structures you're going to need two of them. Ali On Mar 6, 2009, at 1:13 AM, Gabe Black wrote: I think ITBs and DTBs are usually very similar differ in a few key ways like the nx (no execute) bit in x86 for example. In x86 the DTB and ITB classes are basically just wrappers around a common TLB with one translate function, and the DTB's and ITB's version just call that with an extra parameter or two. This should generally work across other ISAs as far as I know. If the translate functions really are radically different, there isn't much overhead in having them both in there and just picking one or the other based on that parameter. I think even the generic TLB that's for SE implementations that don't have an ISA specific TLB yet just looks things up in the page table no matter what your translating. As far as whether to get rid of the separation between the ITB and DTB I think it's a good idea. I can't think of any benefit to having the separation other than that it's already there, and while it hasn't caused any other problems it prevents Korey from having a UTB implementation. We'd likely want to give it parameters which let you independently configure it's ITB and DTB (or UTB) personalities, but that should be pretty easy. This should (knock on wood) be pretty easy to implement and I'd be happy to help. Gabe nathan binkert wrote: How different are ITBs and DTBs anyway? It seems like for a UTB you'd want a single object that handles both ifetch and data translations using a common translate() method, not something that inherits from two different classes. E.g., why not just derive it from TLB? The two translation functions are different because every ISA does some different things for instructions vs data. Think about something like the executable bit. Philosophically, I agree... let's avoid virtual inheritance if at all possible. It's just not a good idea. Ok, so the question is, which of the other alternatives should we do? Gabe (mister TLB expert)? Korey (since this is mips code)? Nate ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev -- -- Korey L Sewell Graduate Student - PhD Candidate Computer Science Engineering University of Michigan ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
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Re: [m5-dev] MIPS UTB and multiple inheritance.
I'll keep both pointers then. I have all the non-ISA bits and X86 converted and I'm trying to test it, but I'm running into a compile error in the stats stuff. Nate? cc1plus: warnings being treated as errors build/X86_SE/base/statistics.hh: In member function 'Stats::VectorDistribution Stats::VectorDistribution::init(Stats::size_type, Stats::Counter, Stats::Counter, Stats::Counter)': build/X86_SE/base/statistics.hh:2498: warning: converting to 'Stats::size_type' from 'double' You have a VectorDistribution stat somewhere, and you're calling its init() function with the first parameter as a float instead of an integer. Nothing magic here, just apply normal debugging techniques. Nate ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] MIPS UTB and multiple inheritance.
On Fri, Mar 6, 2009 at 7:48 AM, nathan binkert n...@binkert.org wrote: Is the following correct? This is in the BaseCPU where it sets up the data and instruction TLBs it's going to use and installs defaults. I'm suspicious that this is actually installing a particular TLB to be the default in all of the CPUs, or in other words all CPUs share the same ITB and DTB. Am I crazy? dtb = Param.SparcDTB(SparcDTB(), Data TLB) itb = Param.SparcITB(SparcITB(), Instruction TLB) No, (at least this is my recollection, confirm please Steve). When you instantiate an object, it essentially does a deep copy of the tree that's there. Yea, that's right. If you want them to share the same object, you need to instantiate two separate objects and explicitly make them point to the same thing. Yes, if you want multiple CPUs to share a TLB you would need to instantiate all the CPUs first and then assign the same TLB to them afterward. Something like this: dtb = Param.SparcDTB(SparcTLB(), Data TLB) itb = Param.SparcITB(Self.dtb, Instruction TLB) should work fine for causing each CPU instance to have a single unified TLB. Steve ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] sparc_fs follow-up
On Thu, Mar 5, 2009 at 5:10 PM, Gabriel Michael Black gbl...@eecs.umich.edu wrote: The change is simple enough that I'll just describe it. This deals solely with the simple CPU, so if your trying to use O3, for example, it won't help you directly. The code here: http://repo.m5sim.org/m5/file/886da6fa6d4a/src/cpu/simple/base.cc#l307 should return if the thread is suspended -or- unallocated. After you change that, I think you'll also run into an assert in the CPU. I just got rid of the assert and haven't had any problems, but that might not be the right thing to do. Gabe I looked at l307 and I don't think it should return if the thread is suspended. It should get activated if the thread is suspended, isn't that right or am I missing something? Polina Quoting Polina Dudnik pdud...@gmail.com: Oh, I see. Do you think you can distribute the partial patch you have? Thank you. Polina On Thu, Mar 5, 2009 at 4:48 PM, Gabriel Michael Black gbl...@eecs.umich.edu wrote: Quoting Polina Dudnik pdud...@gmail.com: On Thu, Mar 5, 2009 at 3:38 PM, Gabriel Michael Black gbl...@eecs.umich.edu wrote: There's actually a bug in the CPU wakeup code which prevents any CPU that isn't activated and then suspended, like SPARCs APs which are suspended directly, from waking up on interrupts, etc. I have a partial fix which I've been using to work around the problem, but we need to come up with a full solution. I don't know if this is what the problem is, but it sounds like it could be. Gabe Are you talking about the seg fault in m5-stable that I get? Or the CPU ids? Polina I was talking about the hang Ali described. If the BP is waiting for an AP to tell it it's alive and the AP never wakes up, the system will likely hang. I ran into that problem in X86_FS. Gabe ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
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Re: [m5-dev] MIPS UTB and multiple inheritance.
nathan binkert wrote: I'll keep both pointers then. I have all the non-ISA bits and X86 converted and I'm trying to test it, but I'm running into a compile error in the stats stuff. Nate? cc1plus: warnings being treated as errors build/X86_SE/base/statistics.hh: In member function 'Stats::VectorDistribution Stats::VectorDistribution::init(Stats::size_type, Stats::Counter, Stats::Counter, Stats::Counter)': build/X86_SE/base/statistics.hh:2498: warning: converting to 'Stats::size_type' from 'double' You have a VectorDistribution stat somewhere, and you're calling its init() function with the first parameter as a float instead of an integer. Nothing magic here, just apply normal debugging techniques. Nate ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev I didn't add or substantially change any stats, though. I just renamed a few. I'll look into this more this evening. Gabe ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] MIPS UTB and multiple inheritance.
That's odd... if it doesn't work that way, I'd consider that a bug. On Fri, Mar 6, 2009 at 10:18 AM, Gabe Black gbl...@eecs.umich.edu wrote: I tried something like this before, and I don't think it works because self.dtb is a paramdesc, not a SparcTLB. What Nate told me to do was to instantiate those objects as regular members first I believe. This was the SouthBridge stuff. Gabe Yes, if you want multiple CPUs to share a TLB you would need to instantiate all the CPUs first and then assign the same TLB to them afterward. Something like this: dtb = Param.SparcDTB(SparcTLB(), Data TLB) itb = Param.SparcITB(Self.dtb, Instruction TLB) should work fine for causing each CPU instance to have a single unified TLB. Steve ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] MIPS UTB and multiple inheritance.
On Fri, Mar 6, 2009 at 10:19 AM, Gabe Black gbl...@eecs.umich.edu wrote: nathan binkert wrote: You have a VectorDistribution stat somewhere, and you're calling its init() function with the first parameter as a float instead of an integer. Nothing magic here, just apply normal debugging techniques. I didn't add or substantially change any stats, though. I just renamed a few. I'll look into this more this evening. It's probably something that was not quite right before but the code let you get away with it, and now with Nate's changes it's a little more strict. Just guessing. Steve ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] MIPS UTB and multiple inheritance.
I took a look at SouthBridge.py to see what you might have been trying... were you trying to access an attribute of the param, like: pic1 = Param.I8259(_pic1, Master PIC) [...] Self.pic1.output [...] I can see where that wouldn't work, as Self.pic1 is a proxy object that merely says look up pic1 later after everything's instantiated. Basically you can't do anything with it other than use it as a default for another param or (if it's numeric) you can do simple math with it (like '2 * Self.clock.latency'). Steve On Fri, Mar 6, 2009 at 10:27 AM, Steve Reinhardt ste...@gmail.com wrote: That's odd... if it doesn't work that way, I'd consider that a bug. On Fri, Mar 6, 2009 at 10:18 AM, Gabe Black gbl...@eecs.umich.edu wrote: I tried something like this before, and I don't think it works because self.dtb is a paramdesc, not a SparcTLB. What Nate told me to do was to instantiate those objects as regular members first I believe. This was the SouthBridge stuff. Gabe Yes, if you want multiple CPUs to share a TLB you would need to instantiate all the CPUs first and then assign the same TLB to them afterward. Something like this: dtb = Param.SparcDTB(SparcTLB(), Data TLB) itb = Param.SparcITB(Self.dtb, Instruction TLB) should work fine for causing each CPU instance to have a single unified TLB. Steve ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] MIPS UTB and multiple inheritance.
I'm heading out the door, but I just tried building X86_SE on the head and it gave me the errors. I didn't think my changes caused them. I have similar problems with ALPHA_SE, and I haven't tried any other targets. gbl...@tater ~/m5/repos/m5.x86fs $ gcc -v Using built-in specs. Target: x86_64-pc-linux-gnu Configured with: /var/tmp/portage/sys-devel/gcc-4.1.2/work/gcc-4.1.2/configure --prefix=/usr --bindir=/usr/x86_64-pc-linux-gnu/gcc-bin/4.1.2 --includedir=/usr/lib/gcc/x86_64-pc-linux-gnu/4.1.2/include --datadir=/usr/share/gcc-data/x86_64-pc-linux-gnu/4.1.2 --mandir=/usr/share/gcc-data/x86_64-pc-linux-gnu/4.1.2/man --infodir=/usr/share/gcc-data/x86_64-pc-linux-gnu/4.1.2/info --with-gxx-include-dir=/usr/lib/gcc/x86_64-pc-linux-gnu/4.1.2/include/g++-v4 --host=x86_64-pc-linux-gnu --build=x86_64-pc-linux-gnu --disable-altivec --enable-nls --without-included-gettext --with-system-zlib --disable-checking --disable-werror --enable-secureplt --enable-multilib --enable-libmudflap --disable-libssp --enable-java-awt=gtk --enable-languages=c,c++,java,treelang,fortran --enable-shared --enable-threads=posix --enable-__cxa_atexit --enable-clocale=gnu Thread model: posix gcc version 4.1.2 (Gentoo 4.1.2 p1.1) gbl...@tater ~/m5/repos/m5.x86fs $ python -V Python 2.5.2 gbl...@tater ~/m5/repos/m5.x86fs $ swig -version SWIG Version 1.3.36 Compiled with x86_64-pc-linux-gnu-g++ [x86_64-pc-linux-gnu] Please see http://www.swig.org for reporting bugs and further information gbl...@tater ~/m5/repos/m5.x86fs $ scons -v SCons by Steven Knight et al.: script: v1.0.0.r3266, 2008/08/12 07:31:01, by knight on bangkok engine: v1.0.0.r3266, 2008/08/12 07:31:01, by knight on bangkok Copyright (c) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008 The SCons Foundation cc1plus: warnings being treated as errors build/X86_SE/base/statistics.hh: In member function 'Stats::VectorDistribution Stats::VectorDistribution::init(Stats::size_type, Stats::Counter, Stats::Counter, Stats::Counter)': build/X86_SE/base/statistics.hh:2498: warning: converting to 'Stats::size_type' from 'double' cc1plus: warnings being treated as errors build/X86_SE/base/statistics.hh: In member function 'Stats::VectorDistribution Stats::VectorDistribution::init(Stats::size_type, Stats::Counter, Stats::Counter, Stats::Counter)': build/X86_SE/base/statistics.hh:2498: warning: converting to 'Stats::size_type' from 'double' cc1plus: warnings being treated as errors build/X86_SE/base/statistics.hh: In member function 'Stats::VectorDistribution Stats::VectorDistribution::init(Stats::size_type, Stats::Counter, Stats::Counter, Stats::Counter)': build/X86_SE/base/statistics.hh:2498: warning: converting to 'Stats::size_type' from 'double' cc1plus: warnings being treated as errors build/X86_SE/base/statistics.hh: In member function 'Stats::VectorDistribution Stats::VectorDistribution::init(Stats::size_type, Stats::Counter, Stats::Counter, Stats::Counter)': build/X86_SE/base/statistics.hh:2498: warning: converting to 'Stats::size_type' from 'double' scons: *** [build/X86_SE/cpu/pc_event.o] Error 1 cc1plus: warnings being treated as errors build/X86_SE/base/statistics.hh: In member function 'Stats::VectorDistribution Stats::VectorDistribution::init(Stats::size_type, Stats::Counter, Stats::Counter, Stats::Counter)': build/X86_SE/base/statistics.hh:2498: warning: converting to 'Stats::size_type' from 'double' scons: *** [build/X86_SE/cpu/thread_context.o] Error 1 cc1plus: warnings being treated as errors build/X86_SE/base/statistics.hh: In member function 'Stats::VectorDistribution Stats::VectorDistribution::init(Stats::size_type, Stats::Counter, Stats::Counter, Stats::Counter)': build/X86_SE/base/statistics.hh:2498: warning: converting to 'Stats::size_type' from 'double' cc1plus: warnings being treated as errors build/X86_SE/base/statistics.hh: In member function 'Stats::VectorDistribution Stats::VectorDistribution::init(Stats::size_type, Stats::Counter, Stats::Counter, Stats::Counter)': build/X86_SE/base/statistics.hh:2498: warning: converting to 'Stats::size_type' from 'double' cc1plus: warnings being treated as errors build/X86_SE/base/statistics.hh: In member function 'Stats::VectorDistribution Stats::VectorDistribution::init(Stats::size_type, Stats::Counter, Stats::Counter, Stats::Counter)': build/X86_SE/base/statistics.hh:2498: warning: converting to 'Stats::size_type' from 'double' Steve Reinhardt wrote: On Fri, Mar 6, 2009 at 10:19 AM, Gabe Black gbl...@eecs.umich.edu wrote: nathan binkert wrote: You have a VectorDistribution stat somewhere, and you're calling its init() function with the first parameter as a float instead of an integer. Nothing magic here, just apply normal debugging techniques. I didn't add or substantially change any stats, though. I just renamed a few. I'll look into this more this evening. It's probably something that was not quite right before but the code let you get away with it, and now with Nate's
Re: [m5-dev] MIPS UTB and multiple inheritance.
That's odd... if it doesn't work that way, I'd consider that a bug. On Fri, Mar 6, 2009 at 10:18 AM, Gabe Black gbl...@eecs.umich.edu wrote: I tried something like this before, and I don't think it works because self.dtb is a paramdesc, not a SparcTLB. What Nate told me to do was to instantiate those objects as regular members first I believe. This was the SouthBridge stuff. I can't remember your specific situation, but I believe that it was special. If you can remind us (or just dig up the title on the e-mail thread), we can see if we can fix it. Nate ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] MIPS UTB and multiple inheritance.
I'll try to figure this out, but I don't get it yet. I'll get an older compiler going... Nate On Fri, Mar 6, 2009 at 10:48 AM, Gabe Black gbl...@eecs.umich.edu wrote: I'm heading out the door, but I just tried building X86_SE on the head and it gave me the errors. I didn't think my changes caused them. I have similar problems with ALPHA_SE, and I haven't tried any other targets. gbl...@tater ~/m5/repos/m5.x86fs $ gcc -v Using built-in specs. Target: x86_64-pc-linux-gnu Configured with: /var/tmp/portage/sys-devel/gcc-4.1.2/work/gcc-4.1.2/configure --prefix=/usr --bindir=/usr/x86_64-pc-linux-gnu/gcc-bin/4.1.2 --includedir=/usr/lib/gcc/x86_64-pc-linux-gnu/4.1.2/include --datadir=/usr/share/gcc-data/x86_64-pc-linux-gnu/4.1.2 --mandir=/usr/share/gcc-data/x86_64-pc-linux-gnu/4.1.2/man --infodir=/usr/share/gcc-data/x86_64-pc-linux-gnu/4.1.2/info --with-gxx-include-dir=/usr/lib/gcc/x86_64-pc-linux-gnu/4.1.2/include/g++-v4 --host=x86_64-pc-linux-gnu --build=x86_64-pc-linux-gnu --disable-altivec --enable-nls --without-included-gettext --with-system-zlib --disable-checking --disable-werror --enable-secureplt --enable-multilib --enable-libmudflap --disable-libssp --enable-java-awt=gtk --enable-languages=c,c++,java,treelang,fortran --enable-shared --enable-threads=posix --enable-__cxa_atexit --enable-clocale=gnu Thread model: posix gcc version 4.1.2 (Gentoo 4.1.2 p1.1) gbl...@tater ~/m5/repos/m5.x86fs $ python -V Python 2.5.2 gbl...@tater ~/m5/repos/m5.x86fs $ swig -version SWIG Version 1.3.36 Compiled with x86_64-pc-linux-gnu-g++ [x86_64-pc-linux-gnu] Please see http://www.swig.org for reporting bugs and further information gbl...@tater ~/m5/repos/m5.x86fs $ scons -v SCons by Steven Knight et al.: script: v1.0.0.r3266, 2008/08/12 07:31:01, by knight on bangkok engine: v1.0.0.r3266, 2008/08/12 07:31:01, by knight on bangkok Copyright (c) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008 The SCons Foundation cc1plus: warnings being treated as errors build/X86_SE/base/statistics.hh: In member function 'Stats::VectorDistribution Stats::VectorDistribution::init(Stats::size_type, Stats::Counter, Stats::Counter, Stats::Counter)': build/X86_SE/base/statistics.hh:2498: warning: converting to 'Stats::size_type' from 'double' cc1plus: warnings being treated as errors build/X86_SE/base/statistics.hh: In member function 'Stats::VectorDistribution Stats::VectorDistribution::init(Stats::size_type, Stats::Counter, Stats::Counter, Stats::Counter)': build/X86_SE/base/statistics.hh:2498: warning: converting to 'Stats::size_type' from 'double' cc1plus: warnings being treated as errors build/X86_SE/base/statistics.hh: In member function 'Stats::VectorDistribution Stats::VectorDistribution::init(Stats::size_type, Stats::Counter, Stats::Counter, Stats::Counter)': build/X86_SE/base/statistics.hh:2498: warning: converting to 'Stats::size_type' from 'double' cc1plus: warnings being treated as errors build/X86_SE/base/statistics.hh: In member function 'Stats::VectorDistribution Stats::VectorDistribution::init(Stats::size_type, Stats::Counter, Stats::Counter, Stats::Counter)': build/X86_SE/base/statistics.hh:2498: warning: converting to 'Stats::size_type' from 'double' scons: *** [build/X86_SE/cpu/pc_event.o] Error 1 cc1plus: warnings being treated as errors build/X86_SE/base/statistics.hh: In member function 'Stats::VectorDistribution Stats::VectorDistribution::init(Stats::size_type, Stats::Counter, Stats::Counter, Stats::Counter)': build/X86_SE/base/statistics.hh:2498: warning: converting to 'Stats::size_type' from 'double' scons: *** [build/X86_SE/cpu/thread_context.o] Error 1 cc1plus: warnings being treated as errors build/X86_SE/base/statistics.hh: In member function 'Stats::VectorDistribution Stats::VectorDistribution::init(Stats::size_type, Stats::Counter, Stats::Counter, Stats::Counter)': build/X86_SE/base/statistics.hh:2498: warning: converting to 'Stats::size_type' from 'double' cc1plus: warnings being treated as errors build/X86_SE/base/statistics.hh: In member function 'Stats::VectorDistribution Stats::VectorDistribution::init(Stats::size_type, Stats::Counter, Stats::Counter, Stats::Counter)': build/X86_SE/base/statistics.hh:2498: warning: converting to 'Stats::size_type' from 'double' cc1plus: warnings being treated as errors build/X86_SE/base/statistics.hh: In member function 'Stats::VectorDistribution Stats::VectorDistribution::init(Stats::size_type, Stats::Counter, Stats::Counter, Stats::Counter)': build/X86_SE/base/statistics.hh:2498: warning: converting to 'Stats::size_type' from 'double' Steve Reinhardt wrote: On Fri, Mar 6, 2009 at 10:19 AM, Gabe Black gbl...@eecs.umich.edu wrote: nathan binkert wrote: You have a VectorDistribution stat somewhere, and you're calling its init() function with the first parameter as a float instead of an integer. Nothing magic here, just apply normal debugging
Re: [m5-dev] scons weirdness
I'm running into this with gem5 now (the problem with canceled or aborted runs) and I think I've tracked down a possible explanation... basically running the test and comparing the outputs are set up as two separate tasks in scons, and the only thing the output comparison task is dependent on is the m5 stats output. So if you don't clear out the old stats file before the run starts, and you abort m5 before it starts writing a new one, the compare outputs task doesn't think it needs to rerun. I'm wondering if there was some change Nate made to stats that caused it to stop clobbering the stats output file when the program aborts. Anyway, the right answer should be to force the task comparison to rerun when any of the m5 outputs changes. I'll give that a try soon and push it if it works. Anecdotally I've had problems with things getting rebuilt unnecessarily too, though usually it doesn't cause the regressions to rerun. It seems to be something to do with python and/or swig. Steve On Tue, Feb 24, 2009 at 1:39 AM, Gabe Black gbl...@eecs.umich.edu wrote: I mentioned this earlier, but scons and regressions are misbehaving, and it's making updating the regressions very annoying. If a run is canceled halfway, scons now assumes it actually finished and was just wrong. I have to go and manually delete the old, incomplete run before it's willing to try again. Also, it seems really anxious to rebuild and rerun tests when it -doesn't- need to. This makes it really annoying to, for instance, see which tests fail, look at the differences, update the results, and verify that they took. If I don't make any mistakes like loosing track of which tests failed, that takes three runs through all of the regressions I'm interested in which takes three times as long as it needs to. Unfortunately I haven't yet managed this minimum, so I've resorted to just updating the stats the first time around and looking at the patch post mortem which is not ideal. If somebody could look at this I'd really appreciate it. If it seems like a local problem, like from when I recently upgraded scons for example, that would be useful information. Gabe ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] MIPS UTB and multiple inheritance.
Nate, I didn't directly implement that UTB part myself but I believe the mips utlb has some different features than a normal tlb which allows them to share one structure. I think that's part of their claim to fame so to speak... Unfortunately, I can't think of the exact mechanism right now, but I'll peek at the code again to be sure... On Fri, Mar 6, 2009 at 10:49 AM, nathan binkert n...@binkert.org wrote: Actually I take that back. That's how it would work if we used inheritance. The BaseTLB doesn't actually know to translate anything, so the UTB would provide it's own implementation directly. You'd still assign it to both ITB and DTB parameters. I still don't understand why there isn't truly just one TLB class. What would the UTB class be for? Nate ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev -- -- Korey L Sewell Graduate Student - PhD Candidate Computer Science Engineering University of Michigan ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] sparc_fs follow-up
Hi Ali!
So, I did run the seg-faulting boot in gdb and realized that in
./build/SPARC_FS/arch/sparc/tlb.cc line 1264 was seg-faulting because it was
reading bits(data,12,8) and not checking to see that they are within the
range of the total thread contexts available and then it was trying to
access the thread context like so threadContexts[bits(data,12,8)]. So, I put
in two lines which checked that the bits read are within the range of
available context and if not I just put in break;. Here's the output I am
getting right now (below). I have also put in the change described by Gabe
into the m5-dev and right now it is seg-faulting for me, so I will run that
in gdb too and try to figure it out.
Polina
m5 slave terminal: Terminal 0
cpu cpu
Sun Fire T2000, No Keyboard
Copyright 2006 Sun Microsystems, Inc. All rights reserved.
OpenBoot 4.23.0, 256 MB memory available, Serial #1122867.
[saidi obp #30]
Ethernet address 0:80:3:de:ad:3, Host ID: 80112233.
Boot device: /virtual-devices/d...@0 File and args: -vV
Loading ufs-file-system package 1.4 04 Aug 1995 13:02:54.
FCode UFS Reader 1.12 00/07/17 15:48:16.
Loading: /platform/SUNW,Sun-Fire-T2000/ufsboot
Loading: /platform/sun4v/ufsboot
device path '/virtual-devi...@100/d...@0:a'
The boot filesystem is logging.
The ufs log is empty and will not be used.
standalone = `kernel/sparcv9/unix', args = `-v'
Elf64 client
Size: 0x76e40+0x1c872+0x3123a Bytes
modpath: /platform/sun4v/kernel /kernel /usr/kernel
module /platform/sun4v/kernel/sparcv9/unix: text at [0x100, 0x1076e3f]
data at 0x180
module misc/sparcv9/krtld: text at [0x1076e40, 0x108f737] data at 0x184dab0
module /platform/sun4v/kernel/sparcv9/genunix: text at [0x108f738,
0x11dd437] data at 0x18531c0
module /platform/sun4v/kernel/misc/sparcv9/platmod: text at [0x11dd438,
0x11dd43f] data at 0x18a4be0
module /platform/sun4v/kernel/cpu/sparcv9/SUNW,UltraSPARC-T1: text at
[0x11dd440, 0x11e06ff] data at 0x18a5300
SunOS Release 5.10 Version Generic_118822-23 64-bit
Copyright 1983-2005 Sun Microsystems, Inc. All rights reserved.
Use is subject to license terms.
Ethernet address = 0:80:3:de:ad:3
mem = 262144K (0x1000)
avail mem = 237879296
root nexus = Sun Fire T2000
pseudo0 at root
pseudo0 is /pseudo
scsi_vhci0 at root
scsi_vhci0 is /scsi_vhci
virtual-device: hsimd0
hsimd0 is /virtual-devi...@100/d...@0
root on /virtual-devi...@100/d...@0:a fstype ufs
pseudo-device: dld0
dld0 is /pseudo/d...@0
cpu0: UltraSPARC-T1 (cpuid 0 clock 5 MHz)
cpu1: UltraSPARC-T1 (cpuid 1 clock 5 MHz)
panic[cpu0]/thread=180e000: cpu1 failed to start (2)
0180b8b0 unix:start_cpu+124 (1, 10166a0, 0, 181cc00, 2, 0)
%l0-3: 0181cc00 01072000
%l4-7: 030001385a20 03000134a0f8 0004 0181a800
0180b960 unix:start_other_cpus+194 (1813000, 2, 1, 0, 1836f28,
1839400)
%l0-3: 0183c5f0 0001 0002
%l4-7: 0001 018b1400 01072000 01016400
0180ba10 genunix:main+1d4 (18a9938, 18a5800, 1836340, 1861c00, 0,
18abc00)
%l0-3: 70002000 0001 018abc00 0002
%l4-7: 018aca28 018ac800 018a9948 018a9800
syncing file systems... done
skipping system dump - no dump device configured
rebooting...
panic - kernel: prom_reboot: reboot call returned!
Program terminated
{0} ok boot disk
ERROR: Last Trap: Fast Data Access MMU Miss
On Thu, Mar 5, 2009 at 2:26 PM, Ali Saidi sa...@umich.edu wrote:
My output looks like this:
M5 compiled Mar 5 2009 13:51:37
M5 revision 632115b48346 5955 default qtip tip start_sparc_2cpu.diff
qbase
M5 started Mar 5 2009 14:03:22
M5 executing on zeep
command line: ./build/SPARC_FS/m5.opt configs/example/fs.py -n 2
Global frequency set at 1 ticks per second
info: No kernel set for full system simulation. Assuming you know what
you're doing...
Listening for t1000 connection on port 3456
0: system.t1000.htod: Real-time clock set to Thu Jan 1
00:00:00 2009
0: system.t1000.htod: Real-time clock set to 1230768000
Listening for t1000 connection on port 3457
0: system.remote_gdb.listener: listening for remote gdb #0 on port 7001
0: system.remote_gdb.listener: listening for remote gdb #1 on port 7000
REAL SIMULATION
info: Entering event queue @ 0. Starting simulation...
hack: Processor 2 is virtual processor 4. Swizzle the numbers(this
will only work for = 2 processors)
hack: Processor 2 is virtual processor 4. Swizzle the numbers(this
will only work for = 2 processors)
info: Ignoring write to SPARC ERROR regsiter
info: Ignoring write to SPARC ERROR regsiter
warn: Don't know what interrupt to clear for console.
For more information see: http://www.m5sim.org/warn/7fe1004f
info: Ignoring write to SPARC ERROR regsiter
info: Ignoring write to SPARC ERROR regsiter
and the console output looks
Re: [m5-dev] sparc_fs follow-up
You probably need to swizzle those bits as well.. turn id 3 into id 1.
Perhaps then it will work.
Ali
On Mar 6, 2009, at 4:44 PM, Polina Dudnik wrote:
Hi Ali!
So, I did run the seg-faulting boot in gdb and realized that in ./
build/SPARC_FS/arch/sparc/tlb.cc line 1264 was seg-faulting because
it was reading bits(data,12,8) and not checking to see that they are
within the range of the total thread contexts available and then it
was trying to access the thread context like so
threadContexts[bits(data,12,8)]. So, I put in two lines which
checked that the bits read are within the range of available context
and if not I just put in break;. Here's the output I am getting
right now (below). I have also put in the change described by Gabe
into the m5-dev and right now it is seg-faulting for me, so I will
run that in gdb too and try to figure it out.
Polina
m5 slave terminal: Terminal 0
cpu cpu
Sun Fire T2000, No Keyboard
Copyright 2006 Sun Microsystems, Inc. All rights reserved.
OpenBoot 4.23.0, 256 MB memory available, Serial #1122867.
[saidi obp #30]
Ethernet address 0:80:3:de:ad:3, Host ID: 80112233.
Boot device: /virtual-devices/d...@0 File and args: -vV
Loading ufs-file-system package 1.4 04 Aug 1995 13:02:54.
FCode UFS Reader 1.12 00/07/17 15:48:16.
Loading: /platform/SUNW,Sun-Fire-T2000/ufsboot
Loading: /platform/sun4v/ufsboot
device path '/virtual-devi...@100/d...@0:a'
The boot filesystem is logging.
The ufs log is empty and will not be used.
standalone = `kernel/sparcv9/unix', args = `-v'
Elf64 client
Size: 0x76e40+0x1c872+0x3123a Bytes
modpath: /platform/sun4v/kernel /kernel /usr/kernel
module /platform/sun4v/kernel/sparcv9/unix: text at [0x100,
0x1076e3f] data at 0x180
module misc/sparcv9/krtld: text at [0x1076e40, 0x108f737] data at
0x184dab0
module /platform/sun4v/kernel/sparcv9/genunix: text at [0x108f738,
0x11dd437] data at 0x18531c0
module /platform/sun4v/kernel/misc/sparcv9/platmod: text at
[0x11dd438, 0x11dd43f] data at 0x18a4be0
module /platform/sun4v/kernel/cpu/sparcv9/SUNW,UltraSPARC-T1: text
at [0x11dd440, 0x11e06ff] data at 0x18a5300
SunOS Release 5.10 Version Generic_118822-23 64-bit
Copyright 1983-2005 Sun Microsystems, Inc. All rights reserved.
Use is subject to license terms.
Ethernet address = 0:80:3:de:ad:3
mem = 262144K (0x1000)
avail mem = 237879296
root nexus = Sun Fire T2000
pseudo0 at root
pseudo0 is /pseudo
scsi_vhci0 at root
scsi_vhci0 is /scsi_vhci
virtual-device: hsimd0
hsimd0 is /virtual-devi...@100/d...@0
root on /virtual-devi...@100/d...@0:a fstype ufs
pseudo-device: dld0
dld0 is /pseudo/d...@0
cpu0: UltraSPARC-T1 (cpuid 0 clock 5 MHz)
cpu1: UltraSPARC-T1 (cpuid 1 clock 5 MHz)
panic[cpu0]/thread=180e000: cpu1 failed to start (2)
0180b8b0 unix:start_cpu+124 (1, 10166a0, 0, 181cc00, 2, 0)
%l0-3: 0181cc00
01072000
%l4-7: 030001385a20 03000134a0f8 0004
0181a800
0180b960 unix:start_other_cpus+194 (1813000, 2, 1, 0,
1836f28, 1839400)
%l0-3: 0183c5f0 0001
0002
%l4-7: 0001 018b1400 01072000
01016400
0180ba10 genunix:main+1d4 (18a9938, 18a5800, 1836340,
1861c00, 0, 18abc00)
%l0-3: 70002000 0001 018abc00
0002
%l4-7: 018aca28 018ac800 018a9948
018a9800
syncing file systems... done
skipping system dump - no dump device configured
rebooting...
panic - kernel: prom_reboot: reboot call returned!
Program terminated
{0} ok boot disk
ERROR: Last Trap: Fast Data Access MMU Miss
On Thu, Mar 5, 2009 at 2:26 PM, Ali Saidi sa...@umich.edu wrote:
My output looks like this:
M5 compiled Mar 5 2009 13:51:37
M5 revision 632115b48346 5955 default qtip tip start_sparc_2cpu.diff
qbase
M5 started Mar 5 2009 14:03:22
M5 executing on zeep
command line: ./build/SPARC_FS/m5.opt configs/example/fs.py -n 2
Global frequency set at 1 ticks per second
info: No kernel set for full system simulation. Assuming you know what
you're doing...
Listening for t1000 connection on port 3456
0: system.t1000.htod: Real-time clock set to Thu Jan 1
00:00:00 2009
0: system.t1000.htod: Real-time clock set to 1230768000
Listening for t1000 connection on port 3457
0: system.remote_gdb.listener: listening for remote gdb #0 on port
7001
0: system.remote_gdb.listener: listening for remote gdb #1 on port
7000
REAL SIMULATION
info: Entering event queue @ 0. Starting simulation...
hack: Processor 2 is virtual processor 4. Swizzle the numbers(this
will only work for = 2 processors)
hack: Processor 2 is virtual processor 4. Swizzle the numbers(this
will only work for = 2 processors)
info: Ignoring write to SPARC ERROR
Re: [m5-dev] sparc_fs follow-up
Can you tell me where you see id 3?
Polina
On Fri, Mar 6, 2009 at 3:49 PM, Ali Saidi sa...@umich.edu wrote:
You probably need to swizzle those bits as well.. turn id 3 into id 1.
Perhaps then it will work.
Ali
On Mar 6, 2009, at 4:44 PM, Polina Dudnik wrote:
Hi Ali!
So, I did run the seg-faulting boot in gdb and realized that in ./
build/SPARC_FS/arch/sparc/tlb.cc line 1264 was seg-faulting because
it was reading bits(data,12,8) and not checking to see that they are
within the range of the total thread contexts available and then it
was trying to access the thread context like so
threadContexts[bits(data,12,8)]. So, I put in two lines which
checked that the bits read are within the range of available context
and if not I just put in break;. Here's the output I am getting
right now (below). I have also put in the change described by Gabe
into the m5-dev and right now it is seg-faulting for me, so I will
run that in gdb too and try to figure it out.
Polina
m5 slave terminal: Terminal 0
cpu cpu
Sun Fire T2000, No Keyboard
Copyright 2006 Sun Microsystems, Inc. All rights reserved.
OpenBoot 4.23.0, 256 MB memory available, Serial #1122867.
[saidi obp #30]
Ethernet address 0:80:3:de:ad:3, Host ID: 80112233.
Boot device: /virtual-devices/d...@0 File and args: -vV
Loading ufs-file-system package 1.4 04 Aug 1995 13:02:54.
FCode UFS Reader 1.12 00/07/17 15:48:16.
Loading: /platform/SUNW,Sun-Fire-T2000/ufsboot
Loading: /platform/sun4v/ufsboot
device path '/virtual-devi...@100/d...@0:a'
The boot filesystem is logging.
The ufs log is empty and will not be used.
standalone = `kernel/sparcv9/unix', args = `-v'
Elf64 client
Size: 0x76e40+0x1c872+0x3123a Bytes
modpath: /platform/sun4v/kernel /kernel /usr/kernel
module /platform/sun4v/kernel/sparcv9/unix: text at [0x100,
0x1076e3f] data at 0x180
module misc/sparcv9/krtld: text at [0x1076e40, 0x108f737] data at
0x184dab0
module /platform/sun4v/kernel/sparcv9/genunix: text at [0x108f738,
0x11dd437] data at 0x18531c0
module /platform/sun4v/kernel/misc/sparcv9/platmod: text at
[0x11dd438, 0x11dd43f] data at 0x18a4be0
module /platform/sun4v/kernel/cpu/sparcv9/SUNW,UltraSPARC-T1: text
at [0x11dd440, 0x11e06ff] data at 0x18a5300
SunOS Release 5.10 Version Generic_118822-23 64-bit
Copyright 1983-2005 Sun Microsystems, Inc. All rights reserved.
Use is subject to license terms.
Ethernet address = 0:80:3:de:ad:3
mem = 262144K (0x1000)
avail mem = 237879296
root nexus = Sun Fire T2000
pseudo0 at root
pseudo0 is /pseudo
scsi_vhci0 at root
scsi_vhci0 is /scsi_vhci
virtual-device: hsimd0
hsimd0 is /virtual-devi...@100/d...@0
root on /virtual-devi...@100/d...@0:a fstype ufs
pseudo-device: dld0
dld0 is /pseudo/d...@0
cpu0: UltraSPARC-T1 (cpuid 0 clock 5 MHz)
cpu1: UltraSPARC-T1 (cpuid 1 clock 5 MHz)
panic[cpu0]/thread=180e000: cpu1 failed to start (2)
0180b8b0 unix:start_cpu+124 (1, 10166a0, 0, 181cc00, 2, 0)
%l0-3: 0181cc00
01072000
%l4-7: 030001385a20 03000134a0f8 0004
0181a800
0180b960 unix:start_other_cpus+194 (1813000, 2, 1, 0,
1836f28, 1839400)
%l0-3: 0183c5f0 0001
0002
%l4-7: 0001 018b1400 01072000
01016400
0180ba10 genunix:main+1d4 (18a9938, 18a5800, 1836340,
1861c00, 0, 18abc00)
%l0-3: 70002000 0001 018abc00
0002
%l4-7: 018aca28 018ac800 018a9948
018a9800
syncing file systems... done
skipping system dump - no dump device configured
rebooting...
panic - kernel: prom_reboot: reboot call returned!
Program terminated
{0} ok boot disk
ERROR: Last Trap: Fast Data Access MMU Miss
On Thu, Mar 5, 2009 at 2:26 PM, Ali Saidi sa...@umich.edu wrote:
My output looks like this:
M5 compiled Mar 5 2009 13:51:37
M5 revision 632115b48346 5955 default qtip tip start_sparc_2cpu.diff
qbase
M5 started Mar 5 2009 14:03:22
M5 executing on zeep
command line: ./build/SPARC_FS/m5.opt configs/example/fs.py -n 2
Global frequency set at 1 ticks per second
info: No kernel set for full system simulation. Assuming you know what
you're doing...
Listening for t1000 connection on port 3456
0: system.t1000.htod: Real-time clock set to Thu Jan 1
00:00:00 2009
0: system.t1000.htod: Real-time clock set to 1230768000
Listening for t1000 connection on port 3457
0: system.remote_gdb.listener: listening for remote gdb #0 on port
7001
0: system.remote_gdb.listener: listening for remote gdb #1 on port
7000
REAL SIMULATION
info: Entering event queue @ 0. Starting simulation...
hack: Processor 2 is virtual processor 4. Swizzle
Re: [m5-dev] sparc_fs follow-up
Oh, never mind, I understand what you are saying. I will do that.
On Fri, Mar 6, 2009 at 3:49 PM, Ali Saidi sa...@umich.edu wrote:
You probably need to swizzle those bits as well.. turn id 3 into id 1.
Perhaps then it will work.
Ali
On Mar 6, 2009, at 4:44 PM, Polina Dudnik wrote:
Hi Ali!
So, I did run the seg-faulting boot in gdb and realized that in ./
build/SPARC_FS/arch/sparc/tlb.cc line 1264 was seg-faulting because
it was reading bits(data,12,8) and not checking to see that they are
within the range of the total thread contexts available and then it
was trying to access the thread context like so
threadContexts[bits(data,12,8)]. So, I put in two lines which
checked that the bits read are within the range of available context
and if not I just put in break;. Here's the output I am getting
right now (below). I have also put in the change described by Gabe
into the m5-dev and right now it is seg-faulting for me, so I will
run that in gdb too and try to figure it out.
Polina
m5 slave terminal: Terminal 0
cpu cpu
Sun Fire T2000, No Keyboard
Copyright 2006 Sun Microsystems, Inc. All rights reserved.
OpenBoot 4.23.0, 256 MB memory available, Serial #1122867.
[saidi obp #30]
Ethernet address 0:80:3:de:ad:3, Host ID: 80112233.
Boot device: /virtual-devices/d...@0 File and args: -vV
Loading ufs-file-system package 1.4 04 Aug 1995 13:02:54.
FCode UFS Reader 1.12 00/07/17 15:48:16.
Loading: /platform/SUNW,Sun-Fire-T2000/ufsboot
Loading: /platform/sun4v/ufsboot
device path '/virtual-devi...@100/d...@0:a'
The boot filesystem is logging.
The ufs log is empty and will not be used.
standalone = `kernel/sparcv9/unix', args = `-v'
Elf64 client
Size: 0x76e40+0x1c872+0x3123a Bytes
modpath: /platform/sun4v/kernel /kernel /usr/kernel
module /platform/sun4v/kernel/sparcv9/unix: text at [0x100,
0x1076e3f] data at 0x180
module misc/sparcv9/krtld: text at [0x1076e40, 0x108f737] data at
0x184dab0
module /platform/sun4v/kernel/sparcv9/genunix: text at [0x108f738,
0x11dd437] data at 0x18531c0
module /platform/sun4v/kernel/misc/sparcv9/platmod: text at
[0x11dd438, 0x11dd43f] data at 0x18a4be0
module /platform/sun4v/kernel/cpu/sparcv9/SUNW,UltraSPARC-T1: text
at [0x11dd440, 0x11e06ff] data at 0x18a5300
SunOS Release 5.10 Version Generic_118822-23 64-bit
Copyright 1983-2005 Sun Microsystems, Inc. All rights reserved.
Use is subject to license terms.
Ethernet address = 0:80:3:de:ad:3
mem = 262144K (0x1000)
avail mem = 237879296
root nexus = Sun Fire T2000
pseudo0 at root
pseudo0 is /pseudo
scsi_vhci0 at root
scsi_vhci0 is /scsi_vhci
virtual-device: hsimd0
hsimd0 is /virtual-devi...@100/d...@0
root on /virtual-devi...@100/d...@0:a fstype ufs
pseudo-device: dld0
dld0 is /pseudo/d...@0
cpu0: UltraSPARC-T1 (cpuid 0 clock 5 MHz)
cpu1: UltraSPARC-T1 (cpuid 1 clock 5 MHz)
panic[cpu0]/thread=180e000: cpu1 failed to start (2)
0180b8b0 unix:start_cpu+124 (1, 10166a0, 0, 181cc00, 2, 0)
%l0-3: 0181cc00
01072000
%l4-7: 030001385a20 03000134a0f8 0004
0181a800
0180b960 unix:start_other_cpus+194 (1813000, 2, 1, 0,
1836f28, 1839400)
%l0-3: 0183c5f0 0001
0002
%l4-7: 0001 018b1400 01072000
01016400
0180ba10 genunix:main+1d4 (18a9938, 18a5800, 1836340,
1861c00, 0, 18abc00)
%l0-3: 70002000 0001 018abc00
0002
%l4-7: 018aca28 018ac800 018a9948
018a9800
syncing file systems... done
skipping system dump - no dump device configured
rebooting...
panic - kernel: prom_reboot: reboot call returned!
Program terminated
{0} ok boot disk
ERROR: Last Trap: Fast Data Access MMU Miss
On Thu, Mar 5, 2009 at 2:26 PM, Ali Saidi sa...@umich.edu wrote:
My output looks like this:
M5 compiled Mar 5 2009 13:51:37
M5 revision 632115b48346 5955 default qtip tip start_sparc_2cpu.diff
qbase
M5 started Mar 5 2009 14:03:22
M5 executing on zeep
command line: ./build/SPARC_FS/m5.opt configs/example/fs.py -n 2
Global frequency set at 1 ticks per second
info: No kernel set for full system simulation. Assuming you know what
you're doing...
Listening for t1000 connection on port 3456
0: system.t1000.htod: Real-time clock set to Thu Jan 1
00:00:00 2009
0: system.t1000.htod: Real-time clock set to 1230768000
Listening for t1000 connection on port 3457
0: system.remote_gdb.listener: listening for remote gdb #0 on port
7001
0: system.remote_gdb.listener: listening for remote gdb #1 on port
7000
REAL SIMULATION
info: Entering event queue @ 0. Starting simulation...
hack: Processor 2 is virtual
[m5-dev] March 11th-30th
To give everyone a heads up, I'm going to have family visiting from March 11th until the 30th and will have very little time for M5 if any. If there's anything important that needs to be done soon, it will need to be done before Tuesday. Gabe ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] MIPS UTB and multiple inheritance.
That may be true, but none of it is actually in the UTB that we have in our tree. All the UTB does is inherit from DTB and ITB and that's it. Although the UTB inheriting from the DTB and ITB seems pointless from the outset, the way it was implemented is that if you can combine the functionality of the ITB and DTB then you have a UTB. So instead of defining the functions separately in a UTB class, you can just inherit from the ITB and DTB classes and note that you would never want to have a separate ITB/DTB class for MIPS anyway. We've already discussed why deriving from the ITB and DTB was desirable as it allowed those base pointers to point the same UTB class. Is that the right implementation? Well, if you are trying to stick to the convention that there has to be an ITB and DTB pointer in each CPU then yes, because how else are you going to mimick the functionality of both in one class? But if we are willing to give BaseTLB pointers in the CPU's and just name those itb and dtb, then I would argue that that is a better solution as described earlier in this thread. Seems like Gabe is doing this anyway (right?), so this should be able to be resolved soon I would think. Nate ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev -- -- Korey L Sewell Graduate Student - PhD Candidate Computer Science Engineering University of Michigan ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] MIPS UTB and multiple inheritance.
Seems like Gabe is doing this anyway (right?) Yes. ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
