[m5-dev] Cron m5t...@zizzer /z/m5/regression/do-regression quick
* build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby passed. * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby passed. * build/ALPHA_SE/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby passed. * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing passed. = Output differences =* build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing passed. * build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing passed. * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-atomic passed. * build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer passed. * build/ALPHA_SE_MOESI_hammer/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer passed. * build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-timing-mp passed. * build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory passed. * build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer passed. * build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory passed. * build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory passed. * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic passed. * build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic passed. * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/inorder-timing passed. * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing passed. * build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-atomic-mp passed. * build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing passed. * build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing passed. * build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory passed. * build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory passed. * build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory passed. * build/ALPHA_SE_MOESI_hammer/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer passed. * build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory passed. * build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory passed. * build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby passed. * build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token passed. * build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token passed. * build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token passed. * build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic passed. * build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual passed. * build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token passed. * build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual passed. * build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing passed. * build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest passed. * build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-atomic passed. * build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing-ruby passed. * build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing passed. * build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/o3-timing passed. * build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/inorder-timing passed. * build/POWER_SE/tests/fast/quick/00.hello/power/linux/o3-timing passed. * build/POWER_SE/tests/fast/quick/00.hello/power/linux/simple-atomic passed. * build/ALPHA_FS/tests/fast/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic passed. * build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing passed. * build/ARM_SE/tests/fast/quick/00.hello/arm/linux/simple-atomic passed. * build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-atomic passed. * build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing-ruby passed. * build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing passed. * build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp passed. *
[m5-dev] changeset in m5: cache: pull CacheSet out of LRU so that other t...
changeset 1d7008e14da6 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=1d7008e14da6
description:
cache: pull CacheSet out of LRU so that other tags can use associative
sets.
diffstat:
6 files changed, 163 insertions(+), 90 deletions(-)
src/mem/cache/blk.hh |5 ++
src/mem/cache/tags/SConscript |1
src/mem/cache/tags/cacheset.cc | 68 ++
src/mem/cache/tags/cacheset.hh | 71
src/mem/cache/tags/lru.cc | 60 ++---
src/mem/cache/tags/lru.hh | 48 +++
diffs (truncated from 409 to 300 lines):
diff -r 862a31349d43 -r 1d7008e14da6 src/mem/cache/blk.hh
--- a/src/mem/cache/blk.hh Sat Feb 20 20:11:58 2010 +
+++ b/src/mem/cache/blk.hh Tue Feb 23 09:33:09 2010 -0800
@@ -98,6 +98,9 @@
*/
int set;
+/** whether this block has been touched */
+bool isTouched;
+
/** Number of references to this block since it was brought in. */
int refCount;
@@ -130,7 +133,7 @@
CacheBlk()
: asid(-1), tag(0), data(0) ,size(0), status(0), whenReady(0),
- set(-1), refCount(0)
+ set(-1), isTouched(false), refCount(0)
{}
/**
diff -r 862a31349d43 -r 1d7008e14da6 src/mem/cache/tags/SConscript
--- a/src/mem/cache/tags/SConscript Sat Feb 20 20:11:58 2010 +
+++ b/src/mem/cache/tags/SConscript Tue Feb 23 09:33:09 2010 -0800
@@ -34,6 +34,7 @@
Source('fa_lru.cc')
Source('iic.cc')
Source('lru.cc')
+Source('cacheset.cc')
SimObject('iic_repl/Repl.py')
Source('iic_repl/gen.cc')
diff -r 862a31349d43 -r 1d7008e14da6 src/mem/cache/tags/cacheset.cc
--- /dev/null Thu Jan 01 00:00:00 1970 +
+++ b/src/mem/cache/tags/cacheset.ccTue Feb 23 09:33:09 2010 -0800
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2009 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * AS IS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Lisa Hsu
+ */
+
+
+#include mem/cache/tags/cacheset.hh
+
+CacheBlk*
+CacheSet::findBlk(Addr tag) const
+{
+for (int i = 0; i assoc; ++i) {
+if (blks[i]-tag == tag blks[i]-isValid()) {
+return blks[i];
+}
+}
+return 0;
+}
+
+void
+CacheSet::moveToHead(CacheBlk *blk)
+{
+// nothing to do if blk is already head
+if (blks[0] == blk)
+return;
+
+// write 'next' block into blks[i], moving up from MRU toward LRU
+// until we overwrite the block we moved to head.
+
+// start by setting up to write 'blk' into blks[0]
+int i = 0;
+CacheBlk *next = blk;
+
+do {
+assert(i assoc);
+// swap blks[i] and next
+CacheBlk *tmp = blks[i];
+blks[i] = next;
+next = tmp;
+++i;
+} while (next != blk);
+}
+
diff -r 862a31349d43 -r 1d7008e14da6 src/mem/cache/tags/cacheset.hh
--- /dev/null Thu Jan 01 00:00:00 1970 +
+++ b/src/mem/cache/tags/cacheset.hhTue Feb 23 09:33:09 2010 -0800
@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2009 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the
[m5-dev] changeset in m5: stats: this makes some fixes to AverageStat and...
changeset 039202aafc0d in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=039202aafc0d
description:
stats: this makes some fixes to AverageStat and AverageVector.
Also, make Formulas work on AverageVector. First, Stat::Average (and
thus
Stats::AverageVector) was broken when coming out of a checkpoint and on
resets,
this fixes that. Formulas also didn't work with AverageVector, but
added
support for that.
diffstat:
2 files changed, 10 insertions(+), 2 deletions(-)
src/base/statistics.hh| 11 +--
src/python/m5/simulate.py |1 +
diffs (60 lines):
diff -r 1d7008e14da6 -r 039202aafc0d src/base/statistics.hh
--- a/src/base/statistics.hhTue Feb 23 09:33:09 2010 -0800
+++ b/src/base/statistics.hhTue Feb 23 09:33:18 2010 -0800
@@ -492,6 +492,8 @@
private:
/** The current count. */
Counter current;
+/** The tick of the last reset */
+Tick lastReset;
/** The total count for all tick. */
mutable Result total;
/** The tick that current last changed. */
@@ -505,7 +507,7 @@
* Build and initializes this stat storage.
*/
AvgStor(Info *info)
-: current(0), total(0), last(0)
+: current(0), lastReset(0), total(0), last(0)
{ }
/**
@@ -547,7 +549,7 @@
result() const
{
assert(last == curTick);
-return (Result)(total + current) / (Result)(curTick + 1);
+return (Result)(total + current) / (Result)(curTick - lastReset + 1);
}
/**
@@ -573,6 +575,7 @@
{
total = 0.0;
last = curTick;
+lastReset = curTick;
}
};
@@ -2551,6 +2554,10 @@
: node(new VectorStatNode(s.info()))
{ }
+Temp(const AverageVector s)
+: node(new VectorStatNode(s.info()))
+{ }
+
/**
*
*/
diff -r 1d7008e14da6 -r 039202aafc0d src/python/m5/simulate.py
--- a/src/python/m5/simulate.py Tue Feb 23 09:33:09 2010 -0800
+++ b/src/python/m5/simulate.py Tue Feb 23 09:33:18 2010 -0800
@@ -148,6 +148,7 @@
print Restoring from checkpoint
internal.core.unserializeAll(dir)
need_resume.append(root)
+stats.reset()
def changeToAtomic(system):
if not isinstance(system, (objects.Root, objects.System)):
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[m5-dev] changeset in m5: cache: Make caches sharing aware and add occupa...
changeset ab05e20dc4a7 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=ab05e20dc4a7
description:
cache: Make caches sharing aware and add occupancy stats.
On the config end, if a shared L2 is created for the system, it is
parameterized to have n sharers as defined by option.num_cpus. In
addition to
making the cache sharing aware so that discriminating tag policies can
make use
of context_ids to make decisions, I added an occupancy AverageStat and
an occ %
stat to each cache so that you could know which contexts are occupying
how much
cache on average, both in terms of blocks and percentage. Note that
since
devices have context_id -1, having an array of occ stats that
correspond to
each context_id will break here, so in FS mode I add an extra bucket
for device
blocks. This bucket is explicitly not added in SE mode in order to not
only
avoid ugliness in the stats.txt file, but to avoid broken stats (some
formulas
break when a bucket is 0).
diffstat:
20 files changed, 126 insertions(+), 23 deletions(-)
configs/example/se.py |1
src/mem/cache/BaseCache.py |1
src/mem/cache/base.cc | 15 ++--
src/mem/cache/base.hh | 48 +--
src/mem/cache/blk.hh|5 ++
src/mem/cache/cache_impl.hh |8 ++--
src/mem/cache/tags/base.cc | 15
src/mem/cache/tags/base.hh | 10 +
src/mem/cache/tags/fa_lru.cc| 14 +++
src/mem/cache/tags/fa_lru.hh|2 -
src/mem/cache/tags/iic.cc |2 -
src/mem/cache/tags/iic.hh |2 -
src/mem/cache/tags/lru.cc | 19 ++
tests/configs/memtest.py|1
tests/configs/o3-timing-mp.py |1
tests/configs/simple-atomic-mp.py |1
tests/configs/simple-timing-mp.py |1
tests/configs/tsunami-o3-dual.py|1
tests/configs/tsunami-simple-atomic-dual.py |1
tests/configs/tsunami-simple-timing-dual.py |1
diffs (truncated from 471 to 300 lines):
diff -r 039202aafc0d -r ab05e20dc4a7 configs/example/se.py
--- a/configs/example/se.py Tue Feb 23 09:33:18 2010 -0800
+++ b/configs/example/se.py Tue Feb 23 09:34:22 2010 -0800
@@ -151,6 +151,7 @@
system.tol2bus = Bus()
system.l2.cpu_side = system.tol2bus.port
system.l2.mem_side = system.membus.port
+system.l2.num_cpus = np
for i in xrange(np):
if options.caches:
diff -r 039202aafc0d -r ab05e20dc4a7 src/mem/cache/BaseCache.py
--- a/src/mem/cache/BaseCache.pyTue Feb 23 09:33:18 2010 -0800
+++ b/src/mem/cache/BaseCache.pyTue Feb 23 09:34:22 2010 -0800
@@ -44,6 +44,7 @@
prioritizeRequests = Param.Bool(False,
always service demand misses first)
repl = Param.Repl(NULL, replacement policy)
+num_cpus = Param.Int(1, number of cpus sharing this cache)
size = Param.MemorySize(capacity in bytes)
forward_snoops = Param.Bool(True,
forward snoops from mem side to cpu side)
diff -r 039202aafc0d -r ab05e20dc4a7 src/mem/cache/base.cc
--- a/src/mem/cache/base.cc Tue Feb 23 09:33:18 2010 -0800
+++ b/src/mem/cache/base.cc Tue Feb 23 09:34:22 2010 -0800
@@ -62,7 +62,8 @@
noTargetMSHR(NULL),
missCount(p-max_miss_count),
drainEvent(NULL),
- addrRange(p-addr_range)
+ addrRange(p-addr_range),
+ _numCpus(p-num_cpus)
{
}
@@ -148,7 +149,11 @@
const string cstr = cmd.toString();
hits[access_idx]
-.init(maxThreadsPerCPU)
+#if FULL_SYSTEM
+.init(_numCpus + 1)
+#else
+.init(_numCpus)
+#endif
.name(name() + . + cstr + _hits)
.desc(number of + cstr + hits)
.flags(total | nozero | nonan)
@@ -185,7 +190,11 @@
const string cstr = cmd.toString();
misses[access_idx]
-.init(maxThreadsPerCPU)
+#if FULL_SYSTEM
+.init(_numCpus + 1)
+#else
+.init(_numCpus)
+#endif
.name(name() + . + cstr + _misses)
.desc(number of + cstr + misses)
.flags(total | nozero | nonan)
diff -r 039202aafc0d -r ab05e20dc4a7 src/mem/cache/base.hh
--- a/src/mem/cache/base.hh Tue Feb 23 09:33:18 2010 -0800
+++ b/src/mem/cache/base.hh Tue Feb 23 09:34:22 2010 -0800
@@ -47,6 +47,7 @@
#include base/statistics.hh
#include base/trace.hh
#include base/types.hh
+#include config/full_system.hh
#include mem/cache/mshr_queue.hh
#include mem/mem_object.hh
#include mem/packet.hh
@@ -219,7 +220,11 @@
* Normally this is all possible memory addresses. */
RangeAddr addrRange;
+/** number of cpus sharing this cache - from config file */
+int _numCpus;
+
public:
+int
