Re: [m5-dev] Review Request: O3: Fixes the way prefetches are handled inside the iew unit. This patch
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/342/#review763 --- Ship it! - Steve On 2010-12-06 16:12:26, Ali Saidi wrote: --- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/342/ --- (Updated 2010-12-06 16:12:26) Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan Binkert. Summary --- O3: Fixes the way prefetches are handled inside the iew unit. This patch prevents the prefetch being added to the instCommit queue twice. Diffs - src/arch/arm/faults.hh 2b5fbdcbfb5d src/arch/arm/tlb.cc 2b5fbdcbfb5d src/cpu/o3/iew_impl.hh 2b5fbdcbfb5d Diff: http://reviews.m5sim.org/r/342/diff Testing --- Thanks, Ali ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] Review Request: O3: Fixes the way prefetches are handled inside the iew unit. This patch
On 2010-12-21 17:29:39, Steve Reinhardt wrote: src/arch/arm/tlb.cc, line 562 http://reviews.m5sim.org/r/342/diff/1/?file=5459#file5459line562 It seems to me like we ought to have a generic check in the CPU models that prevents prefetches to uncacheable locations rather than burying this in the TLB and requiring every ISA to make this check. (Which leads to the question of how/whether this is handled in other ISAs...) Prefetches aren't implemented in Alpha so this hasn't been an issue. I don't know that I agree it should be in a generic place because I don't know that uncachable is equivalent to non-prefetchable. For example, an memory could be marked cacheable but not prefetchable in sparc if memory serves (same is probably true for some ASI accesses). I think the TLB really needs to make the decision because it's got all of the relevant information. - Ali --- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/342/#review559 --- On 2010-12-06 16:12:26, Ali Saidi wrote: --- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/342/ --- (Updated 2010-12-06 16:12:26) Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan Binkert. Summary --- O3: Fixes the way prefetches are handled inside the iew unit. This patch prevents the prefetch being added to the instCommit queue twice. Diffs - src/arch/arm/faults.hh 2b5fbdcbfb5d src/arch/arm/tlb.cc 2b5fbdcbfb5d src/cpu/o3/iew_impl.hh 2b5fbdcbfb5d Diff: http://reviews.m5sim.org/r/342/diff Testing --- Thanks, Ali ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] Review Request: O3: Fixes the way prefetches are handled inside the iew unit. This patch
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/342/#review559 --- src/arch/arm/tlb.cc http://reviews.m5sim.org/r/342/#comment812 It seems to me like we ought to have a generic check in the CPU models that prevents prefetches to uncacheable locations rather than burying this in the TLB and requiring every ISA to make this check. (Which leads to the question of how/whether this is handled in other ISAs...) - Steve On 2010-12-06 16:12:26, Ali Saidi wrote: --- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/342/ --- (Updated 2010-12-06 16:12:26) Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan Binkert. Summary --- O3: Fixes the way prefetches are handled inside the iew unit. This patch prevents the prefetch being added to the instCommit queue twice. Diffs - src/arch/arm/faults.hh 2b5fbdcbfb5d src/arch/arm/tlb.cc 2b5fbdcbfb5d src/cpu/o3/iew_impl.hh 2b5fbdcbfb5d Diff: http://reviews.m5sim.org/r/342/diff Testing --- Thanks, Ali ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] Review Request: O3: Fixes the way prefetches are handled inside the iew unit. This patch
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/342/#review536 --- src/cpu/o3/iew_impl.hh http://reviews.m5sim.org/r/342/#comment793 So the code outside the if block executes normally and the prefetch, if it faults, just silently goes away. - Ali On 2010-12-06 16:12:26, Ali Saidi wrote: --- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/342/ --- (Updated 2010-12-06 16:12:26) Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan Binkert. Summary --- O3: Fixes the way prefetches are handled inside the iew unit. This patch prevents the prefetch being added to the instCommit queue twice. Diffs - src/arch/arm/faults.hh 2b5fbdcbfb5d src/arch/arm/tlb.cc 2b5fbdcbfb5d src/cpu/o3/iew_impl.hh 2b5fbdcbfb5d Diff: http://reviews.m5sim.org/r/342/diff Testing --- Thanks, Ali ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] Review Request: O3: Fixes the way prefetches are handled inside the iew unit. This patch
On 2010-12-09 18:42:27, Ali Saidi wrote: src/cpu/o3/iew_impl.hh, line 1235 http://reviews.m5sim.org/r/342/diff/1/?file=5460#file5460line1235 So the code outside the if block executes normally and the prefetch, if it faults, just silently goes away. Oh, I got it now. I initially thought this was the instruction's execute method returning the fault, but now I see that's not the case (right?). This makes sense now. - Gabe --- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/342/#review536 --- On 2010-12-06 16:12:26, Ali Saidi wrote: --- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/342/ --- (Updated 2010-12-06 16:12:26) Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan Binkert. Summary --- O3: Fixes the way prefetches are handled inside the iew unit. This patch prevents the prefetch being added to the instCommit queue twice. Diffs - src/arch/arm/faults.hh 2b5fbdcbfb5d src/arch/arm/tlb.cc 2b5fbdcbfb5d src/cpu/o3/iew_impl.hh 2b5fbdcbfb5d Diff: http://reviews.m5sim.org/r/342/diff Testing --- Thanks, Ali ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
Re: [m5-dev] Review Request: O3: Fixes the way prefetches are handled inside the iew unit. This patch
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/342/#review522 --- You're commit message isn't formatted properly. src/cpu/o3/iew_impl.hh http://reviews.m5sim.org/r/342/#comment775 Why not just not return a fault in these cases? - Gabe On 2010-12-06 16:12:26, Ali Saidi wrote: --- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/342/ --- (Updated 2010-12-06 16:12:26) Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan Binkert. Summary --- O3: Fixes the way prefetches are handled inside the iew unit. This patch prevents the prefetch being added to the instCommit queue twice. Diffs - src/arch/arm/faults.hh 2b5fbdcbfb5d src/arch/arm/tlb.cc 2b5fbdcbfb5d src/cpu/o3/iew_impl.hh 2b5fbdcbfb5d Diff: http://reviews.m5sim.org/r/342/diff Testing --- Thanks, Ali ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
[m5-dev] Review Request: O3: Fixes the way prefetches are handled inside the iew unit. This patch
--- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/342/ --- Review request for Default, Ali Saidi, Gabe Black, Steve Reinhardt, and Nathan Binkert. Summary --- O3: Fixes the way prefetches are handled inside the iew unit. This patch prevents the prefetch being added to the instCommit queue twice. Diffs - src/arch/arm/faults.hh 2b5fbdcbfb5d src/arch/arm/tlb.cc 2b5fbdcbfb5d src/cpu/o3/iew_impl.hh 2b5fbdcbfb5d Diff: http://reviews.m5sim.org/r/342/diff Testing --- Thanks, Ali ___ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
