changeset 865e37d507c7 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=865e37d507c7
description:
X86: Loosen an assert for x86 and connect the APIC ports when caches
are used.
diffstat:
src/cpu/BaseCPU.py | 4 +++-
1 files changed, 3 insertions(+), 1 deletions(-)
diffs (21 lines):
diff -r 8e8fa2f28f2e -r 865e37d507c7 src/cpu/BaseCPU.py
--- a/src/cpu/BaseCPU.py Tue Nov 23 06:10:17 2010 -0500
+++ b/src/cpu/BaseCPU.py Tue Nov 23 06:11:50 2010 -0500
@@ -167,7 +167,7 @@
exec('self.%s = bus.port' % p)
def addPrivateSplitL1Caches(self, ic, dc):
- assert(len(self._mem_ports) < 6)
+ assert(len(self._mem_ports) < 8)
self.icache = ic
self.dcache = dc
self.icache_port = ic.cpu_side
@@ -176,6 +176,8 @@
if buildEnv['FULL_SYSTEM']:
if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
self._mem_ports += ["itb.walker.port", "dtb.walker.port"]
+ if buildEnv['TARGET_ISA'] == 'x86':
+ self._mem_ports += ["interrupts.pio", "interrupts.int_port"]
def addTwoLevelCacheHierarchy(self, ic, dc, l2c):
self.addPrivateSplitL1Caches(ic, dc)
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