changeset e8c1d4e669a7 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=e8c1d4e669a7
description:
get rid of all instances of readTid() and getThreadNum(). Unify and
eliminate
redundancies with threadId() as their replacement.
diffstat:
5 files changed, 5 insertions(+), 4 deletions(-)
src/cpu/o3/thread_context.hh | 2 ++
src/cpu/simple_thread.hh | 1 -
src/cpu/thread_context.hh | 2 +-
src/cpu/thread_state.cc | 2 +-
src/cpu/thread_state.hh | 2 +-
diffs (truncated from 924 to 300 lines):
diff -r 76abee886def -r e8c1d4e669a7 src/arch/mips/isa/formats/mt.isa
--- a/src/arch/mips/isa/formats/mt.isa Sun Nov 02 21:57:07 2008 -0500
+++ b/src/arch/mips/isa/formats/mt.isa Tue Nov 04 11:35:42 2008 -0500
@@ -196,7 +196,7 @@
def format MT_MFTR(code, *flags) {{
flags += ('IsNonSpeculative', )
-# code = 'std::cerr << curTick << \": T\" <<
xc->tcBase()->getThreadNum() << \": Executing MT INST: ' + name + '\" <<
endl;\n' + code
+# code = 'std::cerr << curTick << \": T\" << xc->tcBase()->threadId()
<< \": Executing MT INST: ' + name + '\" << endl;\n' + code
code += 'if (MT_H == 1) {\n'
code += 'data = bits(data, top_bit, bottom_bit);\n'
@@ -212,7 +212,7 @@
def format MT_MTTR(code, *flags) {{
flags += ('IsNonSpeculative', )
-# code = 'std::cerr << curTick << \": T\" <<
xc->tcBase()->getThreadNum() << \": Executing MT INST: ' + name + '\" <<
endl;\n' + code
+# code = 'std::cerr << curTick << \": T\" << xc->tcBase()->threadId()
<< \": Executing MT INST: ' + name + '\" << endl;\n' + code
iop = InstObjParams(name, Name, 'MTOp', code, flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
diff -r 76abee886def -r e8c1d4e669a7 src/arch/mips/locked_mem.hh
--- a/src/arch/mips/locked_mem.hh Sun Nov 02 21:57:07 2008 -0500
+++ b/src/arch/mips/locked_mem.hh Tue Nov 04 11:35:42 2008 -0500
@@ -52,7 +52,7 @@
xc->setMiscRegNoEffect(LLAddr, req->getPaddr() & ~0xf);
xc->setMiscRegNoEffect(LLFlag, true);
DPRINTF(LLSC, "[tid:%i]: Load-Link Flag Set & Load-Link Address set to
%x.\n",
- req->getThreadNum(), req->getPaddr() & ~0xf);
+ req->threadId(), req->getPaddr() & ~0xf);
}
@@ -94,10 +94,10 @@
if (!lock_flag){
DPRINTF(LLSC, "[tid:%i]: Lock Flag Set, Store Conditional
Failed.\n",
- req->getThreadNum());
+ req->threadId());
} else if ((req->getPaddr() & ~0xf) != lock_addr) {
DPRINTF(LLSC, "[tid:%i]: Load-Link Address Mismatch, Store
Conditional Failed.\n",
- req->getThreadNum());
+ req->threadId());
}
// store conditional failed already, so don't issue it to mem
return false;
diff -r 76abee886def -r e8c1d4e669a7 src/arch/mips/mt.hh
--- a/src/arch/mips/mt.hh Sun Nov 02 21:57:07 2008 -0500
+++ b/src/arch/mips/mt.hh Tue Nov 04 11:35:42 2008 -0500
@@ -78,7 +78,7 @@
// @TODO: Needs to check if this is a branch and if so, take previous
instruction
tc->setMiscReg(TCRestart, tc->readNextPC());
- warn("%i: Halting thread %i in %s @ PC %x, setting restart PC to %x",
curTick, tc->getThreadNum(), tc->getCpuPtr()->name(),
+ warn("%i: Halting thread %i in %s @ PC %x, setting restart PC to %x",
curTick, tc->threadId(), tc->getCpuPtr()->name(),
tc->readPC(), tc->readNextPC());
}
}
@@ -98,7 +98,7 @@
tc->setNextNPC(pc + 8);
tc->activate(0);
- warn("%i: Restoring thread %i in %s @ PC %x", curTick,
tc->getThreadNum(), tc->getCpuPtr()->name(),
+ warn("%i: Restoring thread %i in %s @ PC %x", curTick, tc->threadId(),
tc->getCpuPtr()->name(),
tc->readPC());
}
}
@@ -217,7 +217,7 @@
if (ok == 1) {
unsigned tcstatus = tc->readMiscRegNoEffect(TCStatus);
tc->setMiscReg(TCStatus, insertBits(tcstatus, TCS_A, TCS_A, 0));
- warn("%i: Deactivating Hardware Thread Context #%i", curTick,
tc->getThreadNum());
+ warn("%i: Deactivating Hardware Thread Context #%i", curTick,
tc->threadId());
}
} else if (src_reg > 0) {
if (src_reg && !yield_mask != 0) {
@@ -238,7 +238,7 @@
fault = new ThreadFault();
} else {
//tc->ScheduleOtherThreads();
- //std::cerr << "T" << tc->getThreadNum() << "YIELD: Schedule Other
Threads.\n" << std::endl;
+ //std::cerr << "T" << tc->threadId() << "YIELD: Schedule Other
Threads.\n" << std::endl;
//tc->suspend();
// Save last known PC in TCRestart
// @TODO: Needs to check if this is a branch and if so, take
previous instruction
diff -r 76abee886def -r e8c1d4e669a7 src/arch/mips/utility.cc
--- a/src/arch/mips/utility.cc Sun Nov 02 21:57:07 2008 -0500
+++ b/src/arch/mips/utility.cc Tue Nov 04 11:35:42 2008 -0500
@@ -259,7 +259,7 @@
void
startupCPU(ThreadContext *tc, int cpuId)
{
- tc->activate(0/*tc->getThreadNum()*/);
+ tc->activate(0/*tc->threadId()*/);
}
} // namespace MipsISA
diff -r 76abee886def -r e8c1d4e669a7 src/cpu/base.cc
--- a/src/cpu/base.cc Sun Nov 02 21:57:07 2008 -0500
+++ b/src/cpu/base.cc Tue Nov 04 11:35:42 2008 -0500
@@ -329,6 +329,7 @@
CpuEvent::replaceThreadContext(oldTC, newTC);
assert(newTC->contextId() == oldTC->contextId());
+ assert(newTC->threadId() == oldTC->threadId());
system->replaceThreadContext(newTC, newTC->contextId());
if (DTRACE(Context))
diff -r 76abee886def -r e8c1d4e669a7 src/cpu/base.hh
--- a/src/cpu/base.hh Sun Nov 02 21:57:07 2008 -0500
+++ b/src/cpu/base.hh Tue Nov 04 11:35:42 2008 -0500
@@ -82,7 +82,7 @@
Tick instCnt;
// every cpu has an id, put it in the base cpu
// Set at initialization, only time a cpuId might change is during a
- // takeover (which should be done from within the BaseCPU anyway,
+ // takeover (which should be done from within the BaseCPU anyway,
// therefore no setCpuId() method is provided
int _cpuId;
diff -r 76abee886def -r e8c1d4e669a7 src/cpu/checker/thread_context.hh
--- a/src/cpu/checker/thread_context.hh Sun Nov 02 21:57:07 2008 -0500
+++ b/src/cpu/checker/thread_context.hh Tue Nov 04 11:35:42 2008 -0500
@@ -153,7 +153,7 @@
void profileSample() { return actualTC->profileSample(); }
#endif
- int getThreadNum() { return actualTC->getThreadNum(); }
+ int threadId() { return actualTC->threadId(); }
// @todo: Do I need this?
MachInst getInst() { return actualTC->getInst(); }
diff -r 76abee886def -r e8c1d4e669a7 src/cpu/exetrace.cc
--- a/src/cpu/exetrace.cc Sun Nov 02 21:57:07 2008 -0500
+++ b/src/cpu/exetrace.cc Tue Nov 04 11:35:42 2008 -0500
@@ -59,7 +59,7 @@
outs << (misspeculating ? "-" : "+") << " ";
if (IsOn(ExecThread))
- outs << "T" << thread->getThreadNum() << " : ";
+ outs << "T" << thread->threadId() << " : ";
std::string sym_str;
diff -r 76abee886def -r e8c1d4e669a7 src/cpu/o3/thread_context.hh
--- a/src/cpu/o3/thread_context.hh Sun Nov 02 21:57:07 2008 -0500
+++ b/src/cpu/o3/thread_context.hh Tue Nov 04 11:35:42 2008 -0500
@@ -82,6 +82,10 @@
virtual void setContextId(int id) { thread->setContextId(id); }
+ /** Returns this thread's ID number. */
+ virtual int threadId() { return thread->threadId(); }
+ virtual void setThreadId(int id) { return thread->setThreadId(id); }
+
#if FULL_SYSTEM
/** Returns a pointer to the system. */
virtual System *getSystemPtr() { return cpu->system; }
@@ -152,9 +156,6 @@
/** Samples the function profiling information. */
virtual void profileSample();
#endif
- /** Returns this thread's ID number. */
- virtual int getThreadNum() { return thread->readTid(); }
-
/** Returns the instruction this thread is currently committing.
* Only used when an instruction faults.
*/
@@ -190,36 +191,36 @@
/** Reads this thread's PC. */
virtual uint64_t readPC()
- { return cpu->readPC(thread->readTid()); }
+ { return cpu->readPC(thread->threadId()); }
/** Sets this thread's PC. */
virtual void setPC(uint64_t val);
/** Reads this thread's next PC. */
virtual uint64_t readNextPC()
- { return cpu->readNextPC(thread->readTid()); }
+ { return cpu->readNextPC(thread->threadId()); }
/** Sets this thread's next PC. */
virtual void setNextPC(uint64_t val);
virtual uint64_t readMicroPC()
- { return cpu->readMicroPC(thread->readTid()); }
+ { return cpu->readMicroPC(thread->threadId()); }
virtual void setMicroPC(uint64_t val);
virtual uint64_t readNextMicroPC()
- { return cpu->readNextMicroPC(thread->readTid()); }
+ { return cpu->readNextMicroPC(thread->threadId()); }
virtual void setNextMicroPC(uint64_t val);
/** Reads a miscellaneous register. */
virtual MiscReg readMiscRegNoEffect(int misc_reg)
- { return cpu->readMiscRegNoEffect(misc_reg, thread->readTid()); }
+ { return cpu->readMiscRegNoEffect(misc_reg, thread->threadId()); }
/** Reads a misc. register, including any side-effects the
* read might have as defined by the architecture. */
virtual MiscReg readMiscReg(int misc_reg)
- { return cpu->readMiscReg(misc_reg, thread->readTid()); }
+ { return cpu->readMiscReg(misc_reg, thread->threadId()); }
/** Sets a misc. register. */
virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val);
@@ -257,7 +258,7 @@
/** Executes a syscall in SE mode. */
virtual void syscall(int64_t callnum)
- { return cpu->syscall(callnum, thread->readTid()); }
+ { return cpu->syscall(callnum, thread->threadId()); }
/** Reads the funcExeInst counter. */
virtual Counter readFuncExeInst() { return thread->funcExeInst; }
@@ -271,7 +272,7 @@
virtual uint64_t readNextNPC()
{
- return this->cpu->readNextNPC(this->thread->readTid());
+ return this->cpu->readNextNPC(this->thread->threadId());
}
virtual void setNextNPC(uint64_t val)
@@ -279,7 +280,7 @@
#if THE_ISA == ALPHA_ISA
panic("Not supported on Alpha!");
#endif
- this->cpu->setNextNPC(val, this->thread->readTid());
+ this->cpu->setNextNPC(val, this->thread->threadId());
}
/** This function exits the thread context in the CPU and returns
diff -r 76abee886def -r e8c1d4e669a7 src/cpu/o3/thread_context_impl.hh
--- a/src/cpu/o3/thread_context_impl.hh Sun Nov 02 21:57:07 2008 -0500
+++ b/src/cpu/o3/thread_context_impl.hh Tue Nov 04 11:35:42 2008 -0500
@@ -64,6 +64,7 @@
setStatus(old_context->status());
copyArchRegs(old_context);
setContextId(old_context->contextId());
+ setThreadId(old_context->threadId());
#if !FULL_SYSTEM
thread->funcExeInst = old_context->readFuncExeInst();
@@ -95,7 +96,7 @@
O3ThreadContext<Impl>::activate(int delay)
{
DPRINTF(O3CPU, "Calling activate on Thread Context %d\n",
- getThreadNum());
+ threadId());
if (thread->status() == ThreadContext::Active)
return;
@@ -105,14 +106,14 @@
#endif
if (thread->status() == ThreadContext::Unallocated) {
- cpu->activateWhenReady(thread->readTid());
+ cpu->activateWhenReady(thread->threadId());
return;
}
thread->setStatus(ThreadContext::Active);
// status() == Suspended
- cpu->activateContext(thread->readTid(), delay);
+ cpu->activateContext(thread->threadId(), delay);
}
template <class Impl>
@@ -120,7 +121,7 @@
O3ThreadContext<Impl>::suspend(int delay)
{
DPRINTF(O3CPU, "Calling suspend on Thread Context %d\n",
- getThreadNum());
+ threadId());
if (thread->status() == ThreadContext::Suspended)
return;
@@ -139,7 +140,7 @@
#endif
*/
thread->setStatus(ThreadContext::Suspended);
- cpu->suspendContext(thread->readTid());
+ cpu->suspendContext(thread->threadId());
}
template <class Impl>
@@ -147,13 +148,13 @@
O3ThreadContext<Impl>::deallocate(int delay)
{
DPRINTF(O3CPU, "Calling deallocate on Thread Context %d delay %d\n",
- getThreadNum(), delay);
+ threadId(), delay);
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