Re: [gem5-users] Different cacheline size for instruction cache

[Saivarun R]

Hi Timon,

I too need a different cache-line size, but for the last level cache. Right
now I'm trying to create a class, which will have an array of Cacheblk to
simulate a bigger cacheline. For example, an array of 16 64 byte cacheblks
to simulate a 1KB cache-line size for the last level cache. The challenges
that I'm facing is with regard to fetching, validating and tag storage for
this class. If you have any other idea, it would be helpful.

Regards
Varun.

On Tue, Feb 6, 2018 at 3:58 PM, Timon Evenblij 
wrote:

> Hi all,
>
> I'd like to model an L1 instruction cache with a smaller cache line size
> then the rest of the caches (L1 data cache, L2 cache, ...). After searching
> a little bit, it seems like the cacheline size is specified system-wide,
> and questions related to different cache line sizes for L2 caches have been
> answered that the memory system needs to be (rather significantly) altered
> if needing different cacheline sizes on different levels of the cache.
> However, since my questions is related to the instruction cache only,
> perhaps someone has an idea on how to make this change with little effort?
>
> Kind regards
>
> Timon
>
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Re: [gem5-users] Increasing cacheline size in gem5

[Saivarun R]

Hi Jason,

As you pointed out, I went through the dram_ctrl.cc file and spent some
time designing the implementation. I want to know if what I understood is
correct regarding the implementation or not.

Firstly, there is need of a block structure in dram_ctrl to hold the data.
Then a tag store array for tags. Most importantly, implementing the Master
port functionalities. Though I looked at your tutorials about the ports,
I'm unable to visualize the interactions possible in the current scenario.
I need help in this regard.

And thinking further, I have an idea of creating a wrapper class for the
cacheblks in gem5, which will arrange the cacheblks (of cacheline size 64
bytes) to form a larger "cache-line" (arrange 16 cacheblks to form a 1KB
cache-line size) in the cache. Is it possible to realize different
cacheline sizes with this idea.

Regards
Varun
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Re: [gem5-users] The simulation in two nodes with different ISA i.e. X86 and ARM

[Boyang Xu]

Hi Andreas, 

Thanks for your suggestion! I am going to research COSSIM. :) 

On 2018-02-06 10:40 AM, Andreas Brokalakis wrote:

> If a networked (dual or more nodes) system is to be simulated, COSSIM that 
> extends gem5, does support heterogeneous system simulation out of the box. 
> You may want to try it out: https://github.com/H2020-COSSIM
> 
> Best, Andreas 
> 
> On Tue, Feb 6, 2018 at 6:03 PM, Mohammad Alian  wrote:
> 
> I don't think it's possible in dual mode, but using dist-gem5 you should be 
> able to do that. However, it's not supported out of the box and you need to 
> tweak the scripts to simulate a heterogeneous system. 
> 
> Best, 
> Mohammad 
> 
> On Mon, Feb 5, 2018 at 12:41 PM, Boyang Xu  wrote: 
> 
> Hi, all 
> 
> I would like to know wether GEM5 supports  the simulation in two nodes with 
> different ISAs, i.e. X86 and ARM? 
> 
> Because I want to run bench in a two-nodes gem5, but the nodes have different 
> ISA and system, such as  X86 and ARM, Android and Linux.
> 
> -- 
> Best Regards,
> Boyang Xu
> 
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Re: [gem5-users] The simulation in two nodes with different ISA i.e. X86 and ARM

[Boyang Xu]

Hi, Mohammad 

Thanks for your suggestions! You know, I am researching the dist-gem5.
:) 

On 2018-02-06 08:03 AM, Mohammad Alian wrote:

> I don't think it's possible in dual mode, but using dist-gem5 you should be 
> able to do that. However, it's not supported out of the box and you need to 
> tweak the scripts to simulate a heterogeneous system. 
> 
> Best, 
> Mohammad 
> 
> On Mon, Feb 5, 2018 at 12:41 PM, Boyang Xu  wrote:
> 
>> Hi, all 
>> 
>> I would like to know wether GEM5 supports  the simulation in two nodes with 
>> different ISAs, i.e. X86 and ARM? 
>> 
>> Because I want to run bench in a two-nodes gem5, but the nodes have 
>> different ISA and system, such as  X86 and ARM, Android and Linux.
>> 
>> -- 
>> Best Regards,
>> Boyang Xu
>> 
>> A graduate student in UVIC 
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Boyang Xu

A graduate student in UVIC 

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Re: [gem5-users] The simulation in two nodes with different ISA i.e. X86 and ARM

[Andreas Brokalakis]

If a networked (dual or more nodes) system is to be simulated, COSSIM that
extends gem5, does support heterogeneous system simulation out of the box.
You may want to try it out: https://github.com/H2020-COSSIM

Best,
Andreas

On Tue, Feb 6, 2018 at 6:03 PM, Mohammad Alian 
wrote:

> I don't think it's possible in dual mode, but using dist-gem5 you should
> be able to do that. However, it's not supported out of the box and you need
> to tweak the scripts to simulate a heterogeneous system.
>
> Best,
> Mohammad
>
> On Mon, Feb 5, 2018 at 12:41 PM, Boyang Xu  wrote:
>
>> Hi, all
>>
>> I would like to know wether GEM5 supports  the simulation in two nodes
>> with different ISAs, i.e. X86 and ARM?
>>
>> Because I want to run bench in a two-nodes gem5, but the nodes have
>> different ISA and system, such as  X86 and ARM, Android and Linux.
>> --
>> Best Regards,
>> Boyang Xu
>>
>> A graduate student in UVIC
>>
>> ___
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>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>>
>
>
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Re: [gem5-users] The simulation in two nodes with different ISA i.e. X86 and ARM

[Biruk Yirga]

Hi Boyang,
Yes you can , the only thing you need is, first run you
 scons build/your-architecture/gem5. opt
Regards
Biruk


On Tue, 6 Feb 2018 at 7:03 PM Andreas Brokalakis  wrote:

> Hi Boyang,
>
> can you be a little bit more specific? Is the x86 and ARM node
> interconnected somehow or they are separate and you want to compare the
> results? Do they run the same application? Is it something like a
> client-server application?
>
> Best,
> Andreas
>
> On Mon, Feb 5, 2018 at 8:41 PM, Boyang Xu  wrote:
>
>> Hi, all
>>
>> I would like to know wether GEM5 supports  the simulation in two nodes
>> with different ISAs, i.e. X86 and ARM?
>>
>> Because I want to run bench in a two-nodes gem5, but the nodes have
>> different ISA and system, such as  X86 and ARM, Android and Linux.
>> --
>> Best Regards,
>> Boyang Xu
>>
>> A graduate student in UVIC
>>
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>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>>
>
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 < bir...@etri.re.kr >, birukj...@gmail.com

*ET**R**I*  *한국전자통신연구원*

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Basic Research Center for Software, Building 07-floor 5 office No. 548

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[gem5-users] Different cacheline size for instruction cache

[Timon Evenblij]

Hi all,

I'd like to model an L1 instruction cache with a smaller cache line size
then the rest of the caches (L1 data cache, L2 cache, ...). After searching
a little bit, it seems like the cacheline size is specified system-wide,
and questions related to different cache line sizes for L2 caches have been
answered that the memory system needs to be (rather significantly) altered
if needing different cacheline sizes on different levels of the cache.
However, since my questions is related to the instruction cache only,
perhaps someone has an idea on how to make this change with little effort?

Kind regards

Timon
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Re: [gem5-users] The simulation in two nodes with different ISA i.e. X86 and ARM

[Andreas Brokalakis]

Hi Boyang,

can you be a little bit more specific? Is the x86 and ARM node
interconnected somehow or they are separate and you want to compare the
results? Do they run the same application? Is it something like a
client-server application?

Best,
Andreas

On Mon, Feb 5, 2018 at 8:41 PM, Boyang Xu  wrote:

> Hi, all
>
> I would like to know wether GEM5 supports  the simulation in two nodes
> with different ISAs, i.e. X86 and ARM?
>
> Because I want to run bench in a two-nodes gem5, but the nodes have
> different ISA and system, such as  X86 and ARM, Android and Linux.
> --
> Best Regards,
> Boyang Xu
>
> A graduate student in UVIC
>
> ___
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