Re: [gem5-users] x86 instruction decoding

[Shyam Murthy]

Thanks Gabe, suppose I’m trying to carry out a data flow analysis on the 
program, then quite often I rely on the source registers tagged by gem5. In 
this process, would I not be tracking false dependencies? Is there a way I can 
disable this?

Additionally, have you modelled the same only for LEA op, or for other 
operations too? You were making a call to merge method within the static inst 
class, I assumed this was because x86 has a lot of instructions like ADD AX, 
imm, where the source register is clobbered with the output as well. However, I 
guess primarily you have made calls to the merge method within the static inst 
class to also model partial register updates. 

Thanks,
Shyam

> On Jul 31, 2019, at 9:03 PM, Gabe Black  wrote:
> 
> Hi Shyam. I think the reason is that x86 instructions (and the microops as 
> I've implemented them) can do partial register updates, ie writing to only 
> the lowest byte of a register. In that case, you need the old value to fill 
> in part of the new value of the register. When writing to 32 bits or more of 
> the register (although x86 is full of exceptions), you'd generally not need 
> the old value since you're either writing all 64 bits or zero extending to 64 
> bits in the 32 bit case. That optimization is not implemented, and may or may 
> not be realistic.
> 
> Gabe
> 
> On Tue, Jul 30, 2019 at 2:40 PM Shyam Murthy  > wrote:
> The main reason I am asking is because I am trying to do some dependency 
> analysis in the programs, and false dependencies show up in the process 
> because architecture registers that are destination registers also get 
> populated as source registers (when there is no true dependency). Am I 
> understanding something incorrectly? 
> 
> Thanks,
> Shyam
> 
> On Tue, Jul 30, 2019 at 2:25 PM Shyam Murthy  > wrote:
> Hi Gabe,
> 
> Why is that for some of the operations like ld and lea, the decoding logic 
> within build/X86/arch/generated/decoder-ns.cc.inc, the destination register 
> is also decoded as a src register?
> 
> Thanks,
> Shyam
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Re: [gem5-users] Switching off AVX-512 for running SPEC 2017 in SE mode

[Andrea Mondelli]

Hi

A solution could be to compile SPEC in a docker with Debian Jessie. Sometimes 
the problem comes from unsupported instructions used by system libraries, and 
not the benchmark itself.

Another way is to compile and use an old libc* version, but I found this option 
time-consuming.

Il giorno 25 mar 2019, alle ore 16:51, Kleovoulos Kalaitzidis 
mailto:kleovoulos.kalaitzi...@inria.fr>> ha 
scritto:

Hello,
I want to run the SPEC 2017 workloads in SE mode(X86), but when I do many of 
them run into an error about an unrecognised instruction.


Bests,
A.

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