[gem5-users] Asim benchmarks on gem5

[ABD ALRHMAN ABO ALKHEEL]

I have followed the instructions provided in the gem5.org website to run
the Moby benchmarks on gem5 as follows:

1. Downloaded the Asimbench from
https://bitbucket.org/yongbing_huang/asimbench/downloads/ which contains
the following folders and files:
1. asimbench_android_arm_kernel :
vmlinux.smp.ics.arm.asimbench.2.6.35
2. asimbench_boot_scripts : contains the rcs scripts for
different benchmarks
3. asimbench_disk_image :
ARMv7a-ICS-Android.SMP.Asimbench-v3.img; sdcard-1g-mxplayer.img

2. I have used the "armv7_gem5_v1_1cpu.dtb" and "boot_emm.arm" binaries
downloaded from http://www.gem5.org/dist/current/arm/
aarch-system-20180409.tar.xz.


3. Made the following changes in the config/common/FSConfig.py :

def makeArmSystem(..)
.
self.cf0 = CowIdeDisk(driveID='master')
self.cf2 = CowIdeDisk(driveID='master')
self.cf0.childImage(mdesc.disk())
self.cf2.childImage(disk("sdcard-1g-mxplayer.img"))
# Old platforms have a built-in IDE or CF controller. Default to
# the IDE controller if both exist. New platforms expect the
# storage controller to be added from the config script.
if hasattr(self.realview, "ide"):
#self.realview.ide.disks = [self.cf0]
self.realview.ide.disks = [self.cf0, self.cf2]
elif hasattr(self.realview, "cf_ctrl"):
#self.realview.cf_ctrl.disks = [self.cf0]
self.realview.cf_ctrl.disks = [self.cf0, self.cf2]
else:
self.pci_ide = IdeController(disks=[self.cf0])
pci_devices.append(self.pci_ide)
...

4. Used the following command:

build/ARM/gem5.opt configs/example/fs.py --machine-type=VExpress_EMM 
--os-type=android-ics --cpu-type=MinorCPU --caches 
--kernel=/home/abdkhail/gem5/full_system_images/binaries/vmlinux.smp.ics.arm.asimbench.2.6.35
 
--disk-image=/home/abdkhail/gem5/full_system_images/disks/ARMv7a-ICS-Android.SMP.Asimbench-v3.img
 
--script=/home/abdkhail/gem5/full_system_images/asimbench_boot_scripts/adobe.rcS
 --mem-size=256MB


5. The above commands throw the following error:

gem5 Simulator System.  http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.

gem5 compiled Feb 18 2020 21:57:51
gem5 started Feb 21 2020 00:02:51
gem5 executing on proton, pid 27191
command line: build/ARM/gem5.opt configs/example/fs.py 
--machine-type=VExpress_EMM --os-type=android-ics --cpu-type=MinorCPU --caches 
--kernel=/home/abdkhail/gem5/full_system_images/binaries/vmlinux.smp.ics.arm.asimbench.2.6.35
 
--disk-image=/home/abdkhail/gem5/full_system_images/disks/ARMv7a-ICS-Android.SMP.Asimbench-v3.img
 
--script=/home/abdkhail/gem5/full_system_images/asimbench_boot_scripts/adobe.rcS
 --mem-size=256MB

warn: Can only correctly generate a dtb for VExpress_GEM5_V1 platforms, unless 
custom hardware models have been equipped with generation functionality.
Global frequency set at 1 ticks per second
warn: DRAM device capacity (8192 Mbytes) does not match the address range 
assigned (256 Mbytes)
info: kernel located at: 
/home/abdkhail/gem5/full_system_images/binaries/vmlinux.smp.ics.arm.asimbench.2.6.35
warn: Bootloader entry point 0x10 overriding reset address 0
system.vncserver: Listening for connections on port 5900
system.terminal: Listening for connections on port 3457
0: system.remote_gdb: listening for remote gdb on port 7004
fatal: Kernel is mapped to invalid location (not memory). kernelStart 0x(0) - 
kernelEnd 0x(c04a21ec) 0x8000:0x1404a21ec
Memory Usage: 622056 KBytes

Any help would be appreciated.

Best

___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] CPU scheduler

[Shougang Yuan]

Dear All,

I am trying to find the code about cpu scheduler in SE mode about
multi-core simulation setup. I mean, when we configured several O3 cpus
and assigned a program to each core, how are these cpus been scheduled? Can
anyone provide some details about this? Thanks.

Best regards.

Yuan
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] Exact meaning of ExtMachInst

[Shougang Yuan]

Hi, All,

I am getting confused about "ExtMachInst", it is used a lot in cpu side,
and the only explanation about it I found is in the static_inst.hh, a short
description of "Binary extended machine instruction type". Can anyone
provide more details about this? I am quite confused about this part.
Thanks.

Best regards.

Yuan
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] Advise on Full System O3CPU support by gem5

[Abhishek Singh]

Hello Everyone,

I am looking to do Full System simulations that can support multithreaded
applications. My only requirement is to use O3CPU (detailed/DerivO3CPU).

I wanted to get advice from the community on which ISA and commit can
support FULLY Full System simulations (multi-core, multithreaded) with
O3CPU (detailed/DerivO3CPU)?


Best regards,

Abhishek
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] miss latency cycles is larger than the total CPU cycles

[Sethu Jose]

Hi,

I suppose that the demand_miss_latency parameter is the sum total of all
the miss latencies including the overlapping misses. Also, If this is the
case, I should be looking at average miss latencies rather than overall
miss latencies.

Can someone please confirm this?

Thanks and regards,
Sethu

On Wed, Feb 19, 2020 at 10:14 PM Sethu Jose  wrote:

> Hi,
>
> In my stat.txt file, I see that the miss latency given in cycles is almost
> 15 times greater than the total execution cycles of my gem5 run.
>
> system.switch_cpus.numCycles  31316822936# number of cpu
> cycles simulated
> system.l2.demand_miss_latency::switch_cpus.dtb.walker 476626107789 #
> number of demand (read+write) miss cycles
>
> These results are from simulating with TimingSimpleCPU. However, O3 CPU
> also gives similar results.
>
> Can someone please explain why the miss latencies are larger than the
> number of execution cycles?
>
> Thanks in advance,
>
> Regards
> Sethu
>
>


-- 
Thanks and Regards,
Sethu
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] Stream benchmark mismatch stats

[Jason Lowe-Power]

Hi Majid,

Are you taking into account the instruction fetches?

Cheers,
Jason

On Thu, Feb 20, 2020 at 9:53 AM Majid Jalili  wrote:

> Let me correct myself. If I set the Size to 5K, then there would be total
> of 10K loads (for a[i] and b[i]), so i expect to see 10K/8=1250.
>
> On Thu, Feb 20, 2020 at 11:45 AM Majid Jalili  wrote:
>
>> I am running a simple stream benchmark that does a simple addition:
>>  m5_reset_stats(0,0);
>>  for(int i = 0 ; i > c[i] =a[i]+b[i];
>> m5_dump_stats(0,0);
>>
>> Each element of these arrays is a uint64_t. I turned off prefetchers and
>> only enabled one level of cache. When I run for size of 10K elements,
>> since 8 uint_64 elements can be fit onto a block, I expect to have at most
>> 10K/8=1250 reads from  main memory. However, if I use LRU RP at L1, I see
>> 1792 reads at main memory. If the RP changes to RRRIP, then it would be
>> 1340 reads.
>>
>> I cannot figure out why LRU is doing poorly, while it should be way
>> better. In terms of numCycles, also LRU is slower than RRRIP?
>>
>> Majid
>>
>> ___
> gem5-users mailing list
> gem5-users@gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] Stream benchmark mismatch stats

[Majid Jalili]

Let me correct myself. If I set the Size to 5K, then there would be total
of 10K loads (for a[i] and b[i]), so i expect to see 10K/8=1250.

On Thu, Feb 20, 2020 at 11:45 AM Majid Jalili  wrote:

> I am running a simple stream benchmark that does a simple addition:
>  m5_reset_stats(0,0);
>  for(int i = 0 ; i  c[i] =a[i]+b[i];
> m5_dump_stats(0,0);
>
> Each element of these arrays is a uint64_t. I turned off prefetchers and
> only enabled one level of cache. When I run for size of 10K elements,
> since 8 uint_64 elements can be fit onto a block, I expect to have at most
> 10K/8=1250 reads from  main memory. However, if I use LRU RP at L1, I see
> 1792 reads at main memory. If the RP changes to RRRIP, then it would be
> 1340 reads.
>
> I cannot figure out why LRU is doing poorly, while it should be way
> better. In terms of numCycles, also LRU is slower than RRRIP?
>
> Majid
>
>
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] Stream benchmark mismatch stats

[Majid Jalili]

I am running a simple stream benchmark that does a simple addition:
 m5_reset_stats(0,0);
 for(int i = 0 ; i ___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Re: [gem5-users] RISC-V Multicore Support

[Jason Lowe-Power]

Hi Muhammet,

https://gem5-review.googlesource.com/c/public/gem5/+/9626 has been merged
https://gem5-review.googlesource.com/c/public/gem5/+/9644 has been
abandoned in favor of something else (I'm not fully sure).

Cheers,
Jason

On Thu, Feb 20, 2020 at 2:40 AM Muhammet Abdullah Soytürk <
muhammetabdullahsoyt...@gmail.com> wrote:

> Hi all,
>
> I have seen that multicore support for RISC-V ISA was implemented by some
> researchers from Cornell University. I ran into these
> 
> slides. In one of the slides, they try to pull some changes (
> https://gem5.googlesource.com/public/gem5 refs/changes/26/9626/4 and
> https://gem5.googlesource.com/public/gem5 refs/changes/44/9644/3) from
> the repository which are not available anymore. Are these changes merged in
> upstream gem5?
>
> Best,
> Muhammet
> ___
> gem5-users mailing list
> gem5-users@gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

[gem5-users] RISC-V Multicore Support

[Muhammet Abdullah Soytürk]

Hi all,

I have seen that multicore support for RISC-V ISA was implemented by some
researchers from Cornell University. I ran into these

slides. In one of the slides, they try to pull some changes (
https://gem5.googlesource.com/public/gem5 refs/changes/26/9626/4 and
https://gem5.googlesource.com/public/gem5 refs/changes/44/9644/3) from the
repository which are not available anymore. Are these changes merged in
upstream gem5?

Best,
Muhammet
___
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users