[gem5-users] Re: How event affect curTick?

[Gabe Black via gem5-users]

Conceptually yes. There is usually an event or something an event causes
which tells gem5 to exit, like the last thread of a process exiting, or the
m5 utility running inside a full system simulation telling the simulator it
wants to exit. That will make gem5 return to the config script where it
will usually report that the simulation ended and exit the simulator, but
it can technically go back in and keep processing events. If the simulator
really runs out of events to process all together, time will conceptually
advance to the max time and the simulator will exit.

On Mon, Jun 15, 2020 at 8:42 PM Taiyu Zhou via gem5-users <
gem5-users@gem5.org> wrote:

> Thank you so much,Gabe. So the total time gem5 runs is depending on  the
> final event?
>
> ___
> gem5-users mailing list -- gem5-users@gem5.org
> To unsubscribe send an email to gem5-users-le...@gem5.org
> %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
>
___
gem5-users mailing list -- gem5-users@gem5.org
To unsubscribe send an email to gem5-users-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-users] Re: How event affect curTick?

[Taiyu Zhou via gem5-users]

Thank you so much,Gabe. So the total time gem5 runs is depending on  the final 
event?

___
gem5-users mailing list -- gem5-users@gem5.org
To unsubscribe send an email to gem5-users-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-users] Re: GCN3 GPU Simulation Start-Up Time

[Matt Sinclair via gem5-users]

Hi Dan,

Thanks for the update.  Apologies for the delay, the patch didn't apply
cleanly initially, but I have pushed the patch I promised previously.
Since I'm not sure if you're on the develop branch or the AMD staging
branch, I pushed it to both (there are some differences in code on the
branches, which I hope will be resolved over time as more of the commits
from the staging branch are pushed to develop:

- develop: https://gem5-review.googlesource.com/c/public/gem5/+/30354
- AMD staging: https://gem5-review.googlesource.com/c/amd/gem5/+/30335

I have validated that both of them compile, and asked Kyle R to test that
both of them a) don't break anything that is expected to work publicly with
the GPU and b) hopefully resolve some of the problems (like yours) with
barrier synchronization.  Let us know if this solves your problem too --
fingers crossed.

Thanks,
Matt

On Fri, Jun 12, 2020 at 2:47 PM Daniel Gerzhoy 
wrote:

>   Matt,
>
> It wasn't so much a solution as an explanation. Kyle was running on an r5
> 3600 (3.6-4.2 GHz) whereas I am on a Xeon Gold 5117 @ (2.0 - 2.8 GHz)
>
> The relative difference in clock speed seems to me to be a more reasonable
> explanation for a slowdown from 1-1.5 minutes to ~5min (actual time before
> min) than the 8 min (time before main + exit time) I was seeing before.
>
> I'll update to the latest branch and see if that speeds me up further. I'm
> also going to try running on a faster machine as well though that will take
> some setup-time.
>
> Gaurav,
>
> Thanks for the tip, that will be helpful in the meantime.
>
> Dan
>
> On Fri, Jun 12, 2020 at 3:41 PM GAURAV JAIN  wrote:
>
>> Hi,
>>
>> I am not sure if chiming in now would cause any more confusion, but still
>> giving it a try.
>>
>> @Daniel Gerzhoy  - for hipDeviceSynchronize,
>> as Matt mentioned, they are working on a fix and should have it out there.
>> If you want to, can you try this:
>>
>> hipSetDeviceFlags(hipDeviceScheduleSpin);
>> for (int k = 1; k < dim; k++) {
>> hipLaunchKernelGGL(HIP_KERNEL_NAME(somekernel), grid, threads, 0,
>> 0);
>> hipDeviceSynchronize();
>> }
>>
>> For me, in many cases (not all and in the ones which it didn't work, I
>> got the same error unmapped error as you), this seemed like doing the
>> trick. You should checkout the HEAD and then try this. I am not hoping for
>> it to make any difference but still worth a shot.
>>
>>
>> --
>> *From:* mattdsincl...@gmail.com 
>> *Sent:* Friday, June 12, 2020 2:14 PM
>> *To:* Daniel Gerzhoy 
>> *Cc:* Kyle Roarty ; GAURAV JAIN ;
>> gem5 users mailing list 
>> *Subject:* Re: [gem5-users] GCN3 GPU Simulation Start-Up Time
>>
>> Hi Dan,
>>
>> Glad to hear things are working, and thanks for the tips!  I must admit
>> to not quite following what the solution was though -- are you saying the
>> solution is to replace exit(0)/return with m5_exit()?  I thought your
>> original post said the problem was things taking a really long time before
>> main?  If so, it would seem like something else must have been the
>> problem/solution?
>>
>> Coming to your other questions: I don't recall what exactly the root
>> cause of the hipDeviceSynchronize failure is, but I would definitely
>> recommend updating to the current staging branch head first and testing.  I
>> am also hoping to push a fix today to the barrier bit synchronization --
>> most of the hipDeviceSynchronize-type failures I've seen were due to a bug
>> in my barrier bit implementation.  I'm not sure if this will be the
>> solution to your problem or not, but I can definitely add you as a reviewer
>> and/or point you to it if needed.
>>
>> Not sure about the m5op, hopefully someone else can chime in on that.
>>
>> Thanks,
>> Matt
>>
>> On Fri, Jun 12, 2020 at 12:12 PM Daniel Gerzhoy 
>> wrote:
>>
>> I've figured it out.
>>
>> To measure the time it took to get to main() I put a *return 0; *at the
>> beginning of the function so I wouldn't have to babysit it.
>>
>> I didn't consider that it would also take some time for the simulator to
>> exit, which is where the extra few minutes comes from.
>> Side-note: *m5_exit(0);* instead of a return exits immediately.
>>
>> 5 min is a bit more reasonable of a slowdown for the difference between
>> the two clocks.
>>
>> Two incidental things:
>>
>> 1. Is there a way to have gem5 spit out (real wall-clock) timestamps
>> while it's printing stuff?
>> 2. A while ago I asked about hipDeviceSynchronize(); causing crashes
>> (panic: Tried to read unmapped address 0xffc29f48.). Has this been
>> fixed since?
>>
>> I'm going to update to the head of this branch soon, and eventually to
>> the main branch. If it hasn't been fixed I've created a workaround by
>> stealing the completion signal of the kernel based on its launch id, and
>> manually waiting for it using the HSA interface.
>> Happy to help out and implement this as a m5op (or something) if that
>> would be helpful for you guys.
>>
>> Best,
>>
>> D

[gem5-users] Re: How event affect curTick?

[Gabe Black via gem5-users]

Events are scheduled for a specific time, and it's the event queues job to
go through them in chronological order and call them to do whatever they're
supposed to do. Events happen instantly, in the sense that time does not
pass or change while they're running. They also can't normally affect what
time other events are scheduled. As the event queue processes events, the
current tick is just the time the event which is currently being processed
was scheduled for. New events can't be scheduled for earlier in time, so
time only ever stays in place (if multiple events are scheduled for the
same time) or moves forward.

Gabe

On Mon, Jun 15, 2020 at 4:47 PM Taiyu Zhou via gem5-users <
gem5-users@gem5.org> wrote:

> Hi guys!
> I am using simpleTimingCPU. And I am so confusing on how event affect
> curTick?  I see there is a “setCurTick()” after calling "serviceOne() “ in
> “serviceEvents”. Is this denotes that curTick will be change by event?
> I tried to add a “delayEvent” in addToWriteQueue in dram_ctrl.cc before
> call nextReqEvent. This code likes
> ”
> //before delay
> if(pkt->isWrite()){
> if (!delayEvent.scheduled())
> schedule(delayEvent, curTick()+1);
> }
> //after delay
>   if (!nextReqEvent.scheduled()) {
> DPRINTF(DRAM, "Request scheduled immediately\n");
> schedule(nextReqEvent, curTick());
> }
> ”
> In my understand, I though this will make every events in the eventqueue
> that after “delayEvent” will be delayed 1，because curTIck + 1. And finally
> make gem5 delay 1. But the result shows that there is no affect to those
> event that after delayEvent.
>
> I want to ask
> 1. Is Event insert into eventq on code sequence (which means delayEvent in
> front of nextReqEvent in eventq) or on chronological order(which means 
> nextReqEvent
> in front of delayEvent in eventq) ?
>
> 2. Are there any method to make event after “delayEvent" delay a specified
> time ?
>
> ___
> gem5-users mailing list -- gem5-users@gem5.org
> To unsubscribe send an email to gem5-users-le...@gem5.org
> %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
___
gem5-users mailing list -- gem5-users@gem5.org
To unsubscribe send an email to gem5-users-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-users] Re: Error in building a memobject: "No module named 'MemObject'"

[Gabe Black via gem5-users]

SimObject is a special case and is imported from "SimObject". MemObject
(and all other SimObject subclasses) are imported from m5.objects.*. You're
import should be from m5.objects.MemObject import MemObject.

Gabe

On Mon, Jun 15, 2020 at 5:34 AM Shaikhul Hadi via gem5-users <
gem5-users@gem5.org> wrote:

> I'm trying to build a simple memory object from this link
> . But during
> building gem5.opt,[scons build/X86/gem5.opt] I'm getting this error:
>
>
>
>
>> ModuleNotFoundError: No module named 'MemObject':
>>
> ...
>>
> ...
>>
> File "[Path]/gem5/build/X86/SConscript", line 789:
>> exec('from m5.objects import %s' % modname)
>>   File "", line 1:
>>
>>   File "[Path]/gem5/build/X86/SConscript", line 769:
>> exec(compiled, mod.__dict__)
>>   File "[Path]/gem5/src/simobject/SimpleMemobj.py", line 4:
>> from MemObject import MemObject
>>
>
> My .py,.hh and .cc files are in src/simobject directory. [I used this same
> directory to generate simple SimObject and it worked perfectly.]
>
> I'm using gem5 [SHA: 332a9de33db603e0aefedae1e05134db4257ea3e ] and ubuntu
> 20.04
>
>
> ___
> gem5-users mailing list -- gem5-users@gem5.org
> To unsubscribe send an email to gem5-users-le...@gem5.org
> %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
___
gem5-users mailing list -- gem5-users@gem5.org
To unsubscribe send an email to gem5-users-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-users] How event affect curTick?

[Taiyu Zhou via gem5-users]

Hi guys!
I am using simpleTimingCPU. And I am so confusing on how event affect 
curTick?  I see there is a “setCurTick()” after calling "serviceOne() “ in 
“serviceEvents”. Is this denotes that curTick will be change by event? 
I tried to add a “delayEvent” in addToWriteQueue in dram_ctrl.cc before 
call nextReqEvent. This code likes
”
//before delay
if(pkt->isWrite()){
if (!delayEvent.scheduled())
schedule(delayEvent, curTick()+1);
}
//after delay
if (!nextReqEvent.scheduled()) {
DPRINTF(DRAM, "Request scheduled immediately\n");
schedule(nextReqEvent, curTick());
}
”
In my understand, I though this will make every events in the eventqueue that 
after “delayEvent” will be delayed 1，because curTIck + 1. And finally make gem5 
delay 1. But the result shows that there is no affect to those event that after 
delayEvent.

I want to ask 
1. Is Event insert into eventq on code sequence (which means delayEvent in 
front of nextReqEvent in eventq) or on chronological order(which means 
nextReqEvent in front of delayEvent in eventq) ?

2. Are there any method to make event after “delayEvent" delay a specified time 
?

___
gem5-users mailing list -- gem5-users@gem5.org
To unsubscribe send an email to gem5-users-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-users] Error in building a memobject: "No module named 'MemObject'"

[Shaikhul Hadi via gem5-users]

I'm trying to build a simple memory object from this link
. But during
building gem5.opt,[scons build/X86/gem5.opt] I'm getting this error:




> ModuleNotFoundError: No module named 'MemObject':
>
...
>
...
>
File "[Path]/gem5/build/X86/SConscript", line 789:
> exec('from m5.objects import %s' % modname)
>   File "", line 1:
>
>   File "[Path]/gem5/build/X86/SConscript", line 769:
> exec(compiled, mod.__dict__)
>   File "[Path]/gem5/src/simobject/SimpleMemobj.py", line 4:
> from MemObject import MemObject
>

My .py,.hh and .cc files are in src/simobject directory. [I used this same
directory to generate simple SimObject and it worked perfectly.]

I'm using gem5 [SHA: 332a9de33db603e0aefedae1e05134db4257ea3e ] and ubuntu
20.04
___
gem5-users mailing list -- gem5-users@gem5.org
To unsubscribe send an email to gem5-users-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

[gem5-users] Where modified this gem5 code for checking cpu's number in multiprocess and tracing packet in SE module?

[DaHoon Park via gem5-users]

Hello gem5 users everyone

i would like to know how the benchmark of SPLASH2 communicates between CPU
and dCache in a multi-core environment through Gem5.

Through this link,  http://learning.gem5.org/book/part2/memoryobject.html, I
was able to confirm that communication between CPU and dcache is by packet.

I'm get communication log between CPu and dcache in single core environment.

So I'm trying to take the next step, from multiprocessor environment, gem5
packet does not check the cpu(core) number.

So Where does the packet check each CPU in a multi-core environment?

Also, can I record the log the communication between each cpu and DCache?
___
gem5-users mailing list -- gem5-users@gem5.org
To unsubscribe send an email to gem5-users-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s