[gem5-users] Re: Problem with gem5 memory latency

[Jason Lowe-Power via gem5-users]

Hi everyone,

Just FYI, it's not the best practice to modify files in src/ (e.g.,
src/mem/cache/Cache.py) if you want to change a parameter. Those are
*source* files. Everything in those files can be overridden in the *python
configuration* files. You can simply change something in your config file
if you want to change a parameter. *You should only modify files in src/ if
you are changing or creating new models.*

Hopefully, you'll be seeing some new code in gem5 this summer which will
make this even easier :D.

Cheers,
Jason

On Wed, Jun 17, 2020 at 1:41 PM Muhammet Abdullah Soytürk via gem5-users <
gem5-users@gem5.org> wrote:

> Hi Ahmed,
>
> You could either follow Abhishek's advice and use default configuration
> scripts (se.py or fs.py) or you can create your own script to manipulate
> those options. Writing your own configuration script is recommended (You
> can check this  book to learn how to do
> that). You can change the latency of cache and memory by changing
> src/mem/cache/Cache.py
>  and
> src/mem/DRAMCtrl.py
> 
>  respectively.
>
> Best,
> Muhammet
>
> ahmed khalil via gem5-users , 17 Haz 2020 Çar, 23:01
> tarihinde şunu yazdı:
>
>> Hi, I am a beginner in gem5 ,I  want to change the memory and cache
>> latency of the system simulated using gem5 , but iI didn't find a parameter
>> in the options.py file to use .can you help me ?
>>
>> thanks
>> Ahmed
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[gem5-users] Re: Problem with gem5 memory latency

[Muhammet Abdullah Soytürk via gem5-users]

Hi Ahmed,

You could either follow Abhishek's advice and use default configuration
scripts (se.py or fs.py) or you can create your own script to manipulate
those options. Writing your own configuration script is recommended (You
can check this  book to learn how to do
that). You can change the latency of cache and memory by changing
src/mem/cache/Cache.py
 and
src/mem/DRAMCtrl.py

 respectively.

Best,
Muhammet

ahmed khalil via gem5-users , 17 Haz 2020 Çar, 23:01
tarihinde şunu yazdı:

> Hi, I am a beginner in gem5 ,I  want to change the memory and cache
> latency of the system simulated using gem5 , but iI didn't find a parameter
> in the options.py file to use .can you help me ?
>
> thanks
> Ahmed
> ___
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[gem5-users] Re: Problem with gem5 memory latency

[Abhishek Singh via gem5-users]

Hey.

You can change those parameters for classic cache in config/common/Caches.py
For main memory search for python files in src/mem/ directory, mostly it’s
DRAMCtlr.py file

On Wed, Jun 17, 2020 at 4:00 PM ahmed khalil via gem5-users <
gem5-users@gem5.org> wrote:

> Hi, I am a beginner in gem5 ,I  want to change the memory and cache
> latency of the system simulated using gem5 , but iI didn't find a parameter
> in the options.py file to use .can you help me ?
>
> thanks
> Ahmed
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[gem5-users] Problem with gem5 memory latency

[ahmed khalil via gem5-users]

Hi, I am a beginner in gem5 ,I  want to change the memory and cache latency
of the system simulated using gem5 , but iI didn't find a parameter in the
options.py file to use .can you help me ?

thanks
Ahmed
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[gem5-users] Re: Address incrementing by 8 instead of 4 for int when SimpleMemory is configured as SPM

[Muhammad Aamir Saeed via gem5-users]

Here is the attached disassembly code, which has been generated by the 
-S flag of g++


https://drive.google.com/file/d/1xyuX3-f-JShikUzhPbXJ5VmRJjOX_K3K/view?usp=sharing

On 17.06.2020 19:26, Eliot Moss via gem5-users wrote:

Can you show us a disassembly of your compiled code?  I am wondering
if the compiler may have been really smart and done 10 8-byte stores
instead of 20 4-byte stores to copy data from a constant array ...

Best - Eliot Moss
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[gem5-users] Re: Address incrementing by 8 instead of 4 for int when SimpleMemory is configured as SPM

[Eliot Moss via gem5-users]

Can you show us a disassembly of your compiled code?  I am wondering if the compiler may have been 
really smart and done 10 8-byte stores instead of 20 4-byte stores to copy data from a constant 
array ...


Best - Eliot Moss
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[gem5-users] Re: Address incrementing by 8 instead of 4 for int when SimpleMemory is configured as SPM

[Muhammad Aamir via gem5-users]

Hi Bobby,

In my workload, am simply calling pointer++ once, but I do not know how it
automatically increments as if I am calling pointer++ twice,

here is an example of a very simple version of my workload which also
provides the incorrect address reading

int main()
{
// spm address starts from here
 // uintptr_t address= 10002432; // compiler makes sure to convert this
to binary for the pc
int *Pointer = (int*) 10002432;
int *Pointer2 = Pointer;
   int array[20] ={1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20};
for (int i = 0; i < 20; ++i)
{
*Pointer = array[i];
 Pointer++;
}
printf("size of pointer is%zu\n",sizeof(Pointer) );
for (int i = 0; i < 20; ++i)
{
printf("%d\n",*Pointer2 );
Pointer2++;
}
}

and the config file that I am using is as follows:
https://drive.google.com/file/d/1JIhV89_Fz_paGTOoads5D-11fhq0_pEt/view?usp=sharing

I cannot understand what I am missing or doing wrong.

Thanks
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[gem5-users] Re: Address incrementing by 8 instead of 4 for int when SimpleMemory is configured as SPM

[Bobby Bruce via gem5-users]

Is the problem you are facing in the gem5 code or your guest-code running
in the simulation?

This looks to be a problem in the guest-code. You're calling pointer++
twice, which should, naturally, increment the address by 8. Based on this
information, I do not know why the first incrementation fails to print the
correct address.

--
Dr. Bobby R. Bruce
Room 2235,
Kemper Hall, UC Davis
Davis,
CA, 95616

web: https://www.bobbybruce.net


On Tue, Jun 16, 2020 at 3:26 PM Muhammad Aamir via gem5-users <
gem5-users@gem5.org> wrote:

> Hi everyone,
>
> I have made a system that includes a scratchpad memory(using the class
> Simple Memory as SPM) at the same level as a level 2 cache. The problem
> that am facing is that I can read and write to it in increments of 8 rather
> than 4 for type int, i.e. Pointer++ gives wrong value at an address work
> while Pointer = Pointer + 2 gives me the correct data of a location.
>
> (Pointer++ doesnot cause the address to be incremented unless I call it
> two times)
>
> Would someone kindly guide me as to why this is the case and a
> possible solution. One reason(which is possibly wrong) that I may have, is
> that I cannot use the SimpleMemory class directly, and I have to derive
> another class from it to use it?
>
>
> Attach is a screenshot, when i store an array in the Scratchpad memory. As
> you can see the address is not being incremented for every ++
>
>
> https://drive.google.com/file/d/11arSjlXx1veBTwdmwANl3VhZqLjbIyuh/view?usp=sharing
>
>
> Any help would be highly appreciated.
>
> Thanks
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[gem5-users] Re: GCN3 GPU Simulation Start-Up Time

[Daniel Gerzhoy via gem5-users]

Hey Matt,

Thanks for pushing those changes. I updated the head of the amd staging
branch and tried to run square. The time to get into main stays about the
same (5min) FYI.

But the hipDeviceSynchronize() fails even when I add
hipSetDeviceFlags(hipDeviceScheduleSpin);
unfortunately.

 panic: Tried to read unmapped address 0x1853e78.
PC: 0x752a966b, Instr:   MOV_R_M : ld   rdi, DS:[rbx + 0x8]

Is that PC (0x752a966b( somewhere in the hip code or something?
r in the emulated driver? The line between the simulator code and
guest code is kind of blurry to me around there haha.

Best,

Dan

On Mon, Jun 15, 2020 at 9:59 PM Matt Sinclair 
wrote:

> Hi Dan,
>
> Thanks for the update.  Apologies for the delay, the patch didn't apply
> cleanly initially, but I have pushed the patch I promised previously.
> Since I'm not sure if you're on the develop branch or the AMD staging
> branch, I pushed it to both (there are some differences in code on the
> branches, which I hope will be resolved over time as more of the commits
> from the staging branch are pushed to develop:
>
> - develop: https://gem5-review.googlesource.com/c/public/gem5/+/30354
> - AMD staging: https://gem5-review.googlesource.com/c/amd/gem5/+/30335
>
> I have validated that both of them compile, and asked Kyle R to test that
> both of them a) don't break anything that is expected to work publicly with
> the GPU and b) hopefully resolve some of the problems (like yours) with
> barrier synchronization.  Let us know if this solves your problem too --
> fingers crossed.
>
> Thanks,
> Matt
>
> On Fri, Jun 12, 2020 at 2:47 PM Daniel Gerzhoy 
> wrote:
>
>>   Matt,
>>
>> It wasn't so much a solution as an explanation. Kyle was running on an r5
>> 3600 (3.6-4.2 GHz) whereas I am on a Xeon Gold 5117 @ (2.0 - 2.8 GHz)
>>
>> The relative difference in clock speed seems to me to be a more
>> reasonable explanation for a slowdown from 1-1.5 minutes to ~5min (actual
>> time before min) than the 8 min (time before main + exit time) I was seeing
>> before.
>>
>> I'll update to the latest branch and see if that speeds me up further.
>> I'm also going to try running on a faster machine as well though that will
>> take some setup-time.
>>
>> Gaurav,
>>
>> Thanks for the tip, that will be helpful in the meantime.
>>
>> Dan
>>
>> On Fri, Jun 12, 2020 at 3:41 PM GAURAV JAIN  wrote:
>>
>>> Hi,
>>>
>>> I am not sure if chiming in now would cause any more confusion, but
>>> still giving it a try.
>>>
>>> @Daniel Gerzhoy  - for hipDeviceSynchronize,
>>> as Matt mentioned, they are working on a fix and should have it out there.
>>> If you want to, can you try this:
>>>
>>> hipSetDeviceFlags(hipDeviceScheduleSpin);
>>> for (int k = 1; k < dim; k++) {
>>> hipLaunchKernelGGL(HIP_KERNEL_NAME(somekernel), grid, threads,
>>> 0, 0);
>>> hipDeviceSynchronize();
>>> }
>>>
>>> For me, in many cases (not all and in the ones which it didn't work, I
>>> got the same error unmapped error as you), this seemed like doing the
>>> trick. You should checkout the HEAD and then try this. I am not hoping for
>>> it to make any difference but still worth a shot.
>>>
>>>
>>> --
>>> *From:* mattdsincl...@gmail.com 
>>> *Sent:* Friday, June 12, 2020 2:14 PM
>>> *To:* Daniel Gerzhoy 
>>> *Cc:* Kyle Roarty ; GAURAV JAIN ;
>>> gem5 users mailing list 
>>> *Subject:* Re: [gem5-users] GCN3 GPU Simulation Start-Up Time
>>>
>>> Hi Dan,
>>>
>>> Glad to hear things are working, and thanks for the tips!  I must admit
>>> to not quite following what the solution was though -- are you saying the
>>> solution is to replace exit(0)/return with m5_exit()?  I thought your
>>> original post said the problem was things taking a really long time before
>>> main?  If so, it would seem like something else must have been the
>>> problem/solution?
>>>
>>> Coming to your other questions: I don't recall what exactly the root
>>> cause of the hipDeviceSynchronize failure is, but I would definitely
>>> recommend updating to the current staging branch head first and testing.  I
>>> am also hoping to push a fix today to the barrier bit synchronization --
>>> most of the hipDeviceSynchronize-type failures I've seen were due to a bug
>>> in my barrier bit implementation.  I'm not sure if this will be the
>>> solution to your problem or not, but I can definitely add you as a reviewer
>>> and/or point you to it if needed.
>>>
>>> Not sure about the m5op, hopefully someone else can chime in on that.
>>>
>>> Thanks,
>>> Matt
>>>
>>> On Fri, Jun 12, 2020 at 12:12 PM Daniel Gerzhoy <
>>> daniel.gerz...@gmail.com> wrote:
>>>
>>> I've figured it out.
>>>
>>> To measure the time it took to get to main() I put a *return 0; *at the
>>> beginning of the function so I wouldn't have to babysit it.
>>>
>>> I didn't consider that it would also take some time for the simulator to
>>> exit, which is where the extra few minutes comes from.
>>> Side-note: *m5_exit(0);* instead of a 

[gem5-users] Address incrementing by 8 instead of 4 for int when SimpleMemory is configured as SPM

[Muhammad Aamir via gem5-users]

Hi again everyone,

It would be really nice if someone could assist me as I've tried almost
everything and I cannot figure it out.


Thanks
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