[gem5-users] Instructions on memory bus-O3CPU

2020-07-22 Thread ABD ALRHMAN ABO ALKHEEL via gem5-users
Hi All,

I want to find the memory address that the LD instruction loads data from and 
track the instruction that consumes the data obtained by the load.(i.e. the 
load loads data from a given address into a register X, then the AND 
instruction consumes the data from the memory bus before that data is committed 
to the X register ).  Where can I find the place that the instructions are 
waiting on the memory bus? is it in IEW_impl.hh?

Any help would be appreciated.

Thanks



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[gem5-users] Re: Use checkpoints and fast-forward simultaneously and --outdir option support

2020-07-22 Thread Jinpeng Miao via gem5-users
Saideepak,

Thanks so much for your help. I did not expect the position of the parameter 
would cause the problem. Thanks again!

Best,
Jinpeng


> On Jul 22, 2020, at 9:34 PM, Saideepak Bejawada via gem5-users 
>  wrote:
> 
> Hi Jinpeng,
> 
> I suspect you are giving it in the wrong place. You should specify the option 
> right after 'build/ISA/gem5.opt' in the command. Hope this helps.
> 
> Thanks,
> Saideepak.
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[gem5-users] Re: Use checkpoints and fast-forward simultaneously and --outdir option support

2020-07-22 Thread Saideepak Bejawada via gem5-users
Hi Jinpeng,

I suspect you are giving it in the wrong place. You should specify the option 
right after 'build/ISA/gem5.opt' in the command. Hope this helps.

Thanks,
Saideepak.
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[gem5-users] Re: Use checkpoints and fast-forward simultaneously and --outdir option support

2020-07-22 Thread Jinpeng Miao via gem5-users
Hi Saideepak,

Thanks for trying to help me out. When I use --outdir in the command, I got 
"fs.py: error: no such option: —outdir." Since there is no --outdir option in 
the Options.py. --outdir option is actually belonging to m5.options. So I 
wonder how to insert this parameter from the command line. Thanks.

Best,
Jinpeng___
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[gem5-users] Re: Need help in compiling the kernel

2020-07-22 Thread Ciro Santilli via gem5-users
To compile kernel see e.g.: 
https://raspberrypi.stackexchange.com/questions/192/how-do-i-cross-compile-the-kernel-on-a-ubuntu-host
 but replace arm with arm64 and the compile with the aarch64 one for 64-bit 
arm. All other ISAs are analogous.

The ARM configs are in-tree of the official arm gem5 kernel fork e.g.: 
https://gem5.googlesource.com/arm/linux/+/refs/heads/gem5/v4.15/arch/arm64/configs/gem5_defconfig

The patch at https://www.mail-archive.com/gem5-users@gem5.org/msg06169.html 
contains changes to arch/arm, so it will only work for arm. You could try to 
port. The question then is why it wasn't merged. Maybe CC. Andreas Sandberg.

Possibly related Q to your request: 
https://stackoverflow.com/questions/54133479/accessing-logical-software-thread-id-in-gem5


From: Saideepak Bejawada via gem5-users 
Sent: Wednesday, July 22, 2020 9:32 AM
To: gem5-users@gem5.org 
Cc: Saideepak Bejawada 
Subject: [gem5-users] Need help in compiling the kernel

Hi all,

I am trying to get the PID information from Processinfo: :pid . I got stuck at 
the panic which says 'thread info not compiled into kernel'. I have been 
looking into older posts regarding this.

https://lists.gem5.org/archives/list/gem5-users@gem5.org/thread/MLWTK3SQMOVZ5IKLVV2L24IVPFA5TTLJ/#MLWTK3SQMOVZ5IKLVV2L24IVPFA5TTLJ
https://lists.gem5.org/archives/list/gem5-users@gem5.org/thread/U2UQ6RHTL7VPKQY45SUKCGCT3M5OQAXG/#U2UQ6RHTL7VPKQY45SUKCGCT3M5OQAXG

They say we have to recompile the kernel adding the thread info structure into 
it. I have never compiled a kernel before. Can anyone help me on how to do this?

I found a patch here for the kernel:
https://www.mail-archive.com/gem5-users@gem5.org/msg06169.html
It says it is for ARM. Will the kernel patches be specific for ISAs? Also, how 
can I apply this patch?
Any comments are welcome.
Thanks for your time.

Thanks,
Saideepak.
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[gem5-users] Re: Regarding SMT

2020-07-22 Thread Jason Lowe-Power via gem5-users
Hi Saideepak,

I believe that Arm supports SMT. I'm not sure if *any* ISA's support for
SMT is tested regularly, though. So it may or may not work.

Cheers,
Jason

On Wed, Jul 22, 2020 at 1:07 AM Saideepak Bejawada via gem5-users <
gem5-users@gem5.org> wrote:

> Thanks, Jason.
> I should have given the binaries in ' '. When I do that I am getting the
> error as mentioned in the link. Are there any other ISAs which do not
> support SMT as of know?.
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[gem5-users] Can the packet check the CPU that will arrive?

2020-07-22 Thread DaHoon Park via gem5-users
I want to check which CPU core a particular packet arrives at in a
multi-core system.


Is there any way to check the packet data?

Or should I look at the other part?
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[gem5-users] Regarding "CleanEvict" and "WritebackDirty" in gem5

2020-07-22 Thread Aritra Bagchi via gem5-users
Hi,

What is/are the difference(s) between "*CleanEvict*" requests and "
*WritebackClean*" requests in gem5 cache? The "*CleanEvict*" is considered
to be giving zero for both checks of *isRead( )* and* isWrite()*, whereas,
the "*WritebackClean*" is of type *isWrite( )*. What do they actually mean,
and how are they handled in gem5? Is there documentation specifying what
are the meaning of such different types of memory requests in gem5?

Thanks,
Aritra
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[gem5-users] Need help in compiling the kernel

2020-07-22 Thread Saideepak Bejawada via gem5-users
Hi all,

I am trying to get the PID information from Processinfo: :pid . I got stuck at 
the panic which says 'thread info not compiled into kernel'. I have been 
looking into older posts regarding this. 

https://lists.gem5.org/archives/list/gem5-users@gem5.org/thread/MLWTK3SQMOVZ5IKLVV2L24IVPFA5TTLJ/#MLWTK3SQMOVZ5IKLVV2L24IVPFA5TTLJ
https://lists.gem5.org/archives/list/gem5-users@gem5.org/thread/U2UQ6RHTL7VPKQY45SUKCGCT3M5OQAXG/#U2UQ6RHTL7VPKQY45SUKCGCT3M5OQAXG

They say we have to recompile the kernel adding the thread info structure into 
it. I have never compiled a kernel before. Can anyone help me on how to do this?

I found a patch here for the kernel:
https://www.mail-archive.com/gem5-users@gem5.org/msg06169.html
It says it is for ARM. Will the kernel patches be specific for ISAs? Also, how 
can I apply this patch? 
Any comments are welcome. 
Thanks for your time.

Thanks,
Saideepak.
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[gem5-users] Modelling Non-Volatile Cache in gem5

2020-07-22 Thread Aritra Bagchi via gem5-users
Hi,

How can we model a non-volatile cache, with asymmetric read and write
latency, into gem5? Which files need to be changed? How could we
differentiate between reads and writes?

- Aritra
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[gem5-users] Re: Use checkpoints and fast-forward simultaneously and --outdir option support

2020-07-22 Thread Saideepak Bejawada via gem5-users
Hi Jinpeng,

What is the problem that you are facing with --outdir?

-
Saideepak.
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