[gem5-users] X86KvmCPU segfaults in constructor

2020-07-26 Thread Soramichi Akiyama via gem5-users 
Hi,

I am trying to fast-forward a large workload with X86KvmCPU, but the 
constructor falls into a segmentation fault.
I use the commit tagged with "v20.0.0.0" 
(b1b8af04439240c532d3530a02773b75b9853f77).

The stack trace looks like:
#0  __pthread_kill (threadid=, signo=signo@entry=11) at 
../sysdeps/unix/sysv/linux/pthread_kill.c:56
#1  0x55c0eab76e92 in raiseFatalSignal (signo=signo@entry=11) at 
build/X86/sim/init_signals.cc:105
#2  0x55c0eab76ee9 in segvHandler (sigtype=) at 
build/X86/sim/init_signals.cc:165
#3  
#4  KvmVM::allocVCPUID (this=0x0) at build/X86/cpu/kvm/vm.cc:560
#5  0x55c0eb2ed251 in BaseKvmCPU::BaseKvmCPU (this=0x55c0ecf152a0, 
params=0x55c0ed604e90) at /usr/include/c++/8/ext/new_allocator.h:86
#6  0x55c0eb2f86e1 in X86KvmCPU::X86KvmCPU (this=0x55c0ecf152a0, 
params=0x55c0ed604e90) at build/X86/cpu/kvm/x86_cpu.cc:523
#7  0x55c0eb2f8921 in X86KvmCPUParams::create (this=0x55c0ed604e90) at 
build/X86/cpu/kvm/x86_cpu.cc:1628
...

The KvmVM::allocVCPUID function has only 1 line (return nextVCPUID++),
and accessing nextVCPUID on gdb returns an error:
 (gdb) f 4
 #4  KvmVM::allocVCPUID (this=0x0) at build/X86/cpu/kvm/vm.cc:560
 560   return nextVCPUID++;
 (gdb) p nextVCPUID
 Cannot access memory at address 0xc0

Does anyone have experience of hitting / workarounding this issue?
Given that the address of nextVCPUID (0xc0) looks broken (also that "this" is 
0x0 there), it guess there is an out-of-bound-related bug.
The smallest config that can reproduce this phenomenon is as follows.

import m5
from m5.objects import *

system = System()
system.cpu = X86KvmCPU()

system.cpu.createThreads()
system.cpu.createInterruptController()
system.clk_domain = SrcClockDomain()
system.clk_domain.clock = '1GHz'
system.clk_domain.voltage_domain = VoltageDomain()

root = Root(full_system = False, system = system)
m5.instantiate()

Best regards,

Soramichi
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[gem5-users] Reading data from memory in Gem5

2020-07-26 Thread ABD ALRHMAN ABO ALKHEEL via gem5-users 
Hi All, how to read data from memory in Gem5 using virtual address? Can I read 
data from memory in Gem5  for a specific addresses? If so, should I use the 
virtual address or physical address? Any help would be appreciated. Thanks
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[gem5-users] Re: compute power and performance

2020-07-26 Thread Nikos Nikoleris via gem5-users 

gem5 doesn't provide a power model for the whole system out of the box.
However, it provides the infrastructure for you to hook your own power
model. You will find some very high level information here:
https://www.gem5.org/documentation/general_docs/thermal_model
and here:
http://www.gem5.org/assets/files/ASPLOS2017_gem5_tutorial.pdf from page 122.

Exception to that is the DRAM controller - gem5 uses the drampowerlib to
estimate the DDR core power. If you use a DDR with configured IDD*
values (e.g., DDR3_1600_8x8) then the stats will have an estimation of
the DDR core power.

Nikos

On 25/07/2020 03:35, FARIDEH ZIAEE via gem5-users wrote:

Hi All,

In my project , I need to compute power and performance from output of
gem5 with dvfs.
How can I  do them or which tools can I use for them?

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[gem5-users] Re: How to find the virtual addresses of write requests accepted by the memory controller?

2020-07-26 Thread Nikos Nikoleris via gem5-users 

Hi May,

Packets classified as writes in the memory controller are due to
writebacks from the last-level cache. Writeback packets will have a
physical address but will not have a valid virtual address.

Mapping a physical address to a virtual address in the general case is
not straightforward. In fact, one physical address might map to multiple
virtual addresses.

There are a couple of workarounds which might or might not be applicable
in your use case. For example, you could add a field in the CacheBlk
with the virtual address of the first or last request that accessed it
and then copy it to writeback packet when the block is evicted.

Hope this helps.

Nikos

On 25/07/2020 11:38, may via gem5-users wrote:

Hi,

I want to get the virtual address of the write packet accepted by the
memory controller.
However, I find that only read packets have virtual addresses. For write
packets, pkt->req->hasVaddr() is set false. It only has a physical address.
Is there any method to get the virtual addresses of write requests?

Thanks,
May

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[gem5-users] Re: Fwd: How calculate power in gem5?

2020-07-26 Thread Ciro Santilli via gem5-users 
Hi, is this different from:
https://www.mail-archive.com/gem5-users@gem5.org/msg18093.html If not,
please don't repost so soon, and ping previous thread instead. I'm
preparing to learn/ask around if no one replies.

On Sun, Jul 26, 2020 at 9:08 AM faridehziaee via gem5-users
 wrote:
>
>
>
> Hi All,
>
> In my project , I need to compute power and performance from output of gem5 
> with dvfs.
> How can I  do them or which tools can I use for them?
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[gem5-users] Re: Regarding SMT

2020-07-26 Thread Saideepak Bejawada via gem5-users 
Hi Jason,

How do I run two programs in SMT using FS? 
I did that using se.py but I am not sure how to do it in FS mode?
Somewhere I read, it can be done by running both the processes in the 
background. 
Something like " ./prog1 & and ./prog2  & ".
Do you think that is the correct way? Or is there any standard way to do this? 
Any comments are welcome.

-
Saideepak.
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[gem5-users] Fwd: How calculate power in gem5?

2020-07-26 Thread faridehziaee via gem5-users 

Hi All, In my project , I need to compute power and performance from output of 
gem5 with dvfs. How can I  do them or which tools can I use for them? ___
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[gem5-users] Re: Can the MESI_Three_Level protocol be used in the L1-L2-L3 three-level cache?

2020-07-26 Thread 1154063264--- via gem5-users 
OK, Thank you VIPIN, thank you very much.
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[gem5-users] How to support L1 cache of multiple banks in ruby ​​mode

2020-07-26 Thread 1154063264--- via gem5-users 
In gem5, we can support multiple L2 cache banks through the --num_l2caches 
parameter,  this is mainly implemented by the L1cache controller, such as 
"L1Cache_Controller.cc、MESI_Two_Level-L1cache.sm" etc profile.

I want to support multiple L1 cache banks in gem5, I do not know how to 
implement that? There is no component such as cpu controller in gem5, What file 
do I need to modify to support the L1 cache of multiple banks?
Looking forward to your reply.
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[gem5-users] How to support L1 cache of multiple banks in ruby ​​mode

2020-07-26 Thread 1154063264--- via gem5-users 
In gem5, we can support multiple L2 cache banks through the --num_l2caches 
parameter,  this is mainly implemented by the L1cache controller, such as 
"L1Cache_Controller.cc、MESI_Two_Level-L1cache.sm" etc profile.

I want to support multiple L1 cache banks in gem5, I do not know how to 
implement that? There is no component such as cpu controller in gem5, What file 
do I need to modify to support the L1 cache of multiple banks?
Looking forward to your reply.
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[gem5-users] Re: Can the MESI_Three_Level protocol be used in the L1-L2-L3 three-level cache?

2020-07-26 Thread VIPIN PATEL via gem5-users 
Answer inline.

Regards,
Vipin

On Sun, 26 Jul, 2020, 12:24 1154063264--- via gem5-users, <
gem5-users@gem5.org> wrote:

> Hello, because L0_I, L0_D, and L1 in MESI_Three_Level are private, and L2
> is shared. In my experiment, L1_I, L1_D, and L2 are private, and L3 is
> shared，so I think
> (1) Do I only need to replace all L0 in -L0cache.sm to L1, replace all
> L1 in L1cache.sm to L2, and replace all L2 in L2cache.sm to L3? like this,
> in MESI_Three_Level-L0cache.sm:
> machine(MachineType:L0Cache, "MESI Directory L0 Cache")
>  : Sequencer * sequencer;
>CacheMemory * Icache;
>CacheMemory * Dcache;
>Cycles request_latency := 2;
>Cycles response_latency := 2;
>bool send_evictions;
> I should modify it to this：
> machine(MachineType:L1Cache, "MESI Directory L1 Cache")
>  : Sequencer * sequencer;
>CacheMemory * Icache;
>CacheMemory * Dcache;
>Cycles request_latency := 2;
>Cycles response_latency := 2;
>bool send_evictions;
>

Yes. Make sure to modify the related files and buffer names too.

（2）In addition to changing the variable name, do I need to change the
> functioning of the *.sm files?
> Looking forward to your reply.
>

Depends on use-case. If you are not changing the protocol functioning the
unchanged file will work fine.

Hope this helps.

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