[gem5-users] Re: AMD GCN3 - Can't use single CPU - fatal no spare thread context

[Sampad Mohapatra via gem5-users]

Hi Matt,

Thanks for the clarification.

My issue is I need more than 1 cpu. In this scenario what will be the
effect of this extra cpu
on the coherence traffic, i.e. does it become part of a Core Pair and take
part in coherence exchanges ?
When I am placing cpus in a garnet topology, how do I ignore this
particular cpu ?

Regards,
Sampad


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On Sat, Aug 8, 2020 at 1:08 AM Matt Sinclair via gem5-users <
gem5-users@gem5.org> wrote:

> Hi Sampad,
>
> To literally answer the clone error part: this happens when your
> application needs multiple thread contexts to run.  The failure happens
> when -n 1 is used because the simulator doesn't have enough thread contexts
> to fulfill what the application needs.
>
> Of course, the next logical question is why ROCm needs 2 thread contexts.
> I haven't looked at this specific behavior in several years, but when I dug
> into this in ~2018, I remember this happening because the ROCm stack was
> spawning a thread to check on some details about the system (e.g., it was
> checking if the HCC version was at least version X, because starting with
> that version, the HCC behavior was different).  If you are interested in
> finding the exact call that does this, you can build a debug version of the
> ROCm stack and step through the ROCm stack with gdb while the simulator is
> running.  Eventually you'll get to the instruction in the ROCm stack that
> is doing checks like the one I described above, and you could potentially
> remove that call and return true/false instead as appropriate for the check
> it's doing.  This is what I did previously, although I don't think that
> ROCm patch has been merged into develop or the AMD staging branch yet
> (although like some of the other ROCm patches, it would actually need to be
> placed elsewhere like gem5-resources, not directly in the gem5 repo, since
> it doesn't affect gem5 code).
>
> Alternatively, you can just run with -n 2, as you've found already.  It
> should have very minimal impact on running the application.
>
> Matt
>
> On Fri, Aug 7, 2020 at 11:46 PM Sampad Mohapatra via gem5-users <
> gem5-users@gem5.org> wrote:
>
>> Hi All,
>>
>> Why does the GCN3 model require at least 2 CPUs ?
>> Every time I use a single CPU, gem5 crashes with the following error:
>> *fatal: clone: no spare thread context in system*
>>
>> In contrast, I was able to run the HSAIL model with a single CPU.
>>
>> Thank You,
>> Sampad Mohapatra
>>
>>
>> 
>>  Virus-free.
>> www.avast.com
>> 
>> <#m_-8468723184678421553_m_4482362651241885149_DAB4FAD8-2DD7-40BB-A1B8-4E2AA1F9FDF2>
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[gem5-users] Re: AMD GCN3 - Can't use single CPU - fatal no spare thread context

[Matt Sinclair via gem5-users]

Hi Sampad,

To literally answer the clone error part: this happens when your
application needs multiple thread contexts to run.  The failure happens
when -n 1 is used because the simulator doesn't have enough thread contexts
to fulfill what the application needs.

Of course, the next logical question is why ROCm needs 2 thread contexts.
I haven't looked at this specific behavior in several years, but when I dug
into this in ~2018, I remember this happening because the ROCm stack was
spawning a thread to check on some details about the system (e.g., it was
checking if the HCC version was at least version X, because starting with
that version, the HCC behavior was different).  If you are interested in
finding the exact call that does this, you can build a debug version of the
ROCm stack and step through the ROCm stack with gdb while the simulator is
running.  Eventually you'll get to the instruction in the ROCm stack that
is doing checks like the one I described above, and you could potentially
remove that call and return true/false instead as appropriate for the check
it's doing.  This is what I did previously, although I don't think that
ROCm patch has been merged into develop or the AMD staging branch yet
(although like some of the other ROCm patches, it would actually need to be
placed elsewhere like gem5-resources, not directly in the gem5 repo, since
it doesn't affect gem5 code).

Alternatively, you can just run with -n 2, as you've found already.  It
should have very minimal impact on running the application.

Matt

On Fri, Aug 7, 2020 at 11:46 PM Sampad Mohapatra via gem5-users <
gem5-users@gem5.org> wrote:

> Hi All,
>
> Why does the GCN3 model require at least 2 CPUs ?
> Every time I use a single CPU, gem5 crashes with the following error:
> *fatal: clone: no spare thread context in system*
>
> In contrast, I was able to run the HSAIL model with a single CPU.
>
> Thank You,
> Sampad Mohapatra
>
>
> 
>  Virus-free.
> www.avast.com
> 
> <#m_4482362651241885149_DAB4FAD8-2DD7-40BB-A1B8-4E2AA1F9FDF2>
> ___
> gem5-users mailing list -- gem5-users@gem5.org
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[gem5-users] AMD GCN3 - Can't use single CPU - fatal no spare thread context

[Sampad Mohapatra via gem5-users]

Hi All,

Why does the GCN3 model require at least 2 CPUs ?
Every time I use a single CPU, gem5 crashes with the following error:
*fatal: clone: no spare thread context in system*

In contrast, I was able to run the HSAIL model with a single CPU.

Thank You,
Sampad Mohapatra


Virus-free.
www.avast.com

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[gem5-users] Re: Reading from memory in Gem5

[ABD ALRHMAN ABO ALKHEEL via gem5-users]

Hello Jason,

It is for a debug-only read and I want to see what is in the main memory only 
not in the cache.

Thanks for your email, I really appreciate that.


From: Jason Lowe-Power 
Sent: Friday, August 7, 2020 5:52 PM
To: ABD ALRHMAN ABO ALKHEEL 
Cc: gem5 users mailing list 
Subject: Re: [gem5-users] Re: Reading from memory in Gem5

Hello,

Is this a debug-only read or are you trying to simulate the timing for the 
read? Do you want to see what's in the main memory or do you want to see the 
up-to-date values in the caches? The answers to these questions will drive what 
type of access you want to make and what object you want to use to make the 
access.

Generally, you can simply construct a packet and send a request of any size to 
any object. See 
http://www.gem5.org/documentation/learning_gem5/part2/simplecache/ for details 
on how to send/receive memory requests.

Cheers,
Jason

PS: There is no need to send multiple emails. People will either respond or 
they won't. Spamming the list (and individuals) will *decrease* the chance of a 
response due to causing people to get frustrated. Please don't stop asking 
questions! But it's important to be polite when asking them :).

On Thu, Aug 6, 2020 at 12:44 PM ABD ALRHMAN ABO ALKHEEL 
mailto:abdkeel...@hotmail.com>> wrote:
Hi Jason,

I want to clarify what I want to do; I want to run a program on gem5 (in SE 
mode) for 1M instructions and I want to save the memory addresses that every LD 
instruction loads data from ( I can get those addresses from the pushRequest 
method in the lsq) http://doxygen.gem5.org/release/current/classLSQ.html and 
saving those addresses in a table (map). After a specific time for example 
(every100k instructions), I want to access the memory to read the data from 
those addresses. For instance, let us assume that the address that load 
instruction loads data from it is (0x78226e68), can I read the content of 
this memory address? Also can I read the 256 bytes of this address 
(0x78226e00-0x78226eff)? If so, how?

Thanks



From: Jason Lowe-Power mailto:ja...@lowepower.com>>
Sent: Tuesday, August 4, 2020 4:41 PM
To: ABD ALRHMAN ABO ALKHEEL 
mailto:abdkeel...@hotmail.com>>; gem5 users mailing 
list mailto:gem5-users@gem5.org>>
Subject: Re: [gem5-users] Re: Reading from memory in Gem5

Hello,

First of all, please reply to the users list, not directly to the person who 
responded. This allows everyone to see answers and/or chime in and help.

Second, the page you linked is out of date. Please use the main gem5 website 
for all of the up to date documentation (e.g., 
http://doxygen.gem5.org/release/current/classLSQUnit.html)

Third, I still don't fully understand what your goals are. However, you can use 
the system port (actually, I think I was wrong before, you should use the 
"getPort" function, not "getSystemPort") to make functional (or debug) accesses 
to the memory. You can create a `Packet` with a `Request` and send a functional 
request across the port (i.e., call sendFunctional(pkt)). You can use either 
virtual (in SE mode) or physical address (in both modes). I am sure there are 
some caveats to using virtual addresses, but I don't know exactly what they are.

If you're trying to make new timing accesses, then you should use the main 
"dcache_port" and "icache_port" that are connected to the CPU. Again, you can 
construct a Packet object with a Request and send it across the port (e.g., 
sendTimingReq(pkt)).

You may want to read up on the details of how gem5's memory objects work: 
http://www.gem5.org/documentation/learning_gem5/part2/memoryobject/

Cheers,
Jason



On Mon, Aug 3, 2020 at 1:15 PM ABD ALRHMAN ABO ALKHEEL 
mailto:abdkeel...@hotmail.com>> wrote:
Hi Jason,

Thanks for your email.

What I want to do is finding the memory address that the LD instruction loads 
data from ( I can get the physical and virtual address from the Read method in 
the lsqunit)http://pages.cs.wisc.edu/~swilson/gem5-docs/classLSQUnit.html and 
saving those addresses. After a specific time, I want to access the memory to 
read the data from those addresses. Can I use getSystemPort function to access 
the memory and read the data from those addresses? If so, should I use the 
virtual address or the physical address?

Thanks



From: Jason Lowe-Power mailto:ja...@lowepower.com>>
Sent: Monday, August 3, 2020 3:26 PM
To: gem5 users mailing list mailto:gem5-users@gem5.org>>
Cc: gem5-users 
mailto:gem5-users-boun...@gem5.org>>; ABD ALRHMAN 
ABO ALKHEEL mailto:abdkeel...@hotmail.com>>
Subject: Re: [gem5-users] Re: Reading from memory in Gem5

Hello,

This sounds like you probably want to use "functional" accesses. These are 
built for introspection and debugging, which is what it sounds like you want to 
do. Using the System object, there is a `getSystemPort` function that will 
return a gem5 port that you can use with functional 

[gem5-users] Re: Reading from memory in Gem5

[ABD ALRHMAN ABO ALKHEEL via gem5-users]

Hi Jason,

Thanks for your email.

I am sorry about that, I sent the second email in order to update the first one 
about reading the memory with 256 bytes size of the data not to make any 
spamming.

Thanks


From: Jason Lowe-Power 
Sent: Friday, August 7, 2020 5:52 PM
To: ABD ALRHMAN ABO ALKHEEL 
Cc: gem5 users mailing list 
Subject: Re: [gem5-users] Re: Reading from memory in Gem5

Hello,

Is this a debug-only read or are you trying to simulate the timing for the 
read? Do you want to see what's in the main memory or do you want to see the 
up-to-date values in the caches? The answers to these questions will drive what 
type of access you want to make and what object you want to use to make the 
access.

Generally, you can simply construct a packet and send a request of any size to 
any object. See 
http://www.gem5.org/documentation/learning_gem5/part2/simplecache/ for details 
on how to send/receive memory requests.

Cheers,
Jason

PS: There is no need to send multiple emails. People will either respond or 
they won't. Spamming the list (and individuals) will *decrease* the chance of a 
response due to causing people to get frustrated. Please don't stop asking 
questions! But it's important to be polite when asking them :).

On Thu, Aug 6, 2020 at 12:44 PM ABD ALRHMAN ABO ALKHEEL 
mailto:abdkeel...@hotmail.com>> wrote:
Hi Jason,

I want to clarify what I want to do; I want to run a program on gem5 (in SE 
mode) for 1M instructions and I want to save the memory addresses that every LD 
instruction loads data from ( I can get those addresses from the pushRequest 
method in the lsq) http://doxygen.gem5.org/release/current/classLSQ.html and 
saving those addresses in a table (map). After a specific time for example 
(every100k instructions), I want to access the memory to read the data from 
those addresses. For instance, let us assume that the address that load 
instruction loads data from it is (0x78226e68), can I read the content of 
this memory address? Also can I read the 256 bytes of this address 
(0x78226e00-0x78226eff)? If so, how?

Thanks



From: Jason Lowe-Power mailto:ja...@lowepower.com>>
Sent: Tuesday, August 4, 2020 4:41 PM
To: ABD ALRHMAN ABO ALKHEEL 
mailto:abdkeel...@hotmail.com>>; gem5 users mailing 
list mailto:gem5-users@gem5.org>>
Subject: Re: [gem5-users] Re: Reading from memory in Gem5

Hello,

First of all, please reply to the users list, not directly to the person who 
responded. This allows everyone to see answers and/or chime in and help.

Second, the page you linked is out of date. Please use the main gem5 website 
for all of the up to date documentation (e.g., 
http://doxygen.gem5.org/release/current/classLSQUnit.html)

Third, I still don't fully understand what your goals are. However, you can use 
the system port (actually, I think I was wrong before, you should use the 
"getPort" function, not "getSystemPort") to make functional (or debug) accesses 
to the memory. You can create a `Packet` with a `Request` and send a functional 
request across the port (i.e., call sendFunctional(pkt)). You can use either 
virtual (in SE mode) or physical address (in both modes). I am sure there are 
some caveats to using virtual addresses, but I don't know exactly what they are.

If you're trying to make new timing accesses, then you should use the main 
"dcache_port" and "icache_port" that are connected to the CPU. Again, you can 
construct a Packet object with a Request and send it across the port (e.g., 
sendTimingReq(pkt)).

You may want to read up on the details of how gem5's memory objects work: 
http://www.gem5.org/documentation/learning_gem5/part2/memoryobject/

Cheers,
Jason



On Mon, Aug 3, 2020 at 1:15 PM ABD ALRHMAN ABO ALKHEEL 
mailto:abdkeel...@hotmail.com>> wrote:
Hi Jason,

Thanks for your email.

What I want to do is finding the memory address that the LD instruction loads 
data from ( I can get the physical and virtual address from the Read method in 
the lsqunit)http://pages.cs.wisc.edu/~swilson/gem5-docs/classLSQUnit.html and 
saving those addresses. After a specific time, I want to access the memory to 
read the data from those addresses. Can I use getSystemPort function to access 
the memory and read the data from those addresses? If so, should I use the 
virtual address or the physical address?

Thanks



From: Jason Lowe-Power mailto:ja...@lowepower.com>>
Sent: Monday, August 3, 2020 3:26 PM
To: gem5 users mailing list mailto:gem5-users@gem5.org>>
Cc: gem5-users 
mailto:gem5-users-boun...@gem5.org>>; ABD ALRHMAN 
ABO ALKHEEL mailto:abdkeel...@hotmail.com>>
Subject: Re: [gem5-users] Re: Reading from memory in Gem5

Hello,

This sounds like you probably want to use "functional" accesses. These are 
built for introspection and debugging, which is what it sounds like you want to 
do. Using the System object, there is a `getSystemPort` function that will 
return a 

[gem5-users] Re: Error only occurs with higher number of clusters and cpus

[Sebastian Block via gem5-users]

 
Thank you very much. I will give Ruby a try.Am Freitag, 7. August 2020, 
16:41:12 MESZ hat Ciro Santilli  Folgendes geschrieben:  
 
 #yiv9784044512 P {margin-top:0;margin-bottom:0;}It might be the same as: 
https://gem5.atlassian.net/browse/GEM5-711 I want to investigate that soon 
hopefully.
If you try Ruby and it fails, please open a separate bug, we want it to work as 
wellFrom: Sebastian Block via gem5-users 
Sent: Friday, August 7, 2020 9:27 AM
To: gem5-users@gem5.org 
Cc: Sebastian Block 
Subject: [gem5-users] Error only occurs with higher number of clusters and cpus 
Hi all,
My gem5 project consists of clusters and some cpus in the clusters, simulating 
them in fs mode.Simulating in atomic mode always works. While simulating less 
then 6 cpus works perfectly fine in timing mode, with more then 6 the 
simulation crashes with the error: 
panic: panic condition (pkt->needsWritable() != pkt->isInvalidate()) && 
!pkt->req->isCacheMaintenance() occurred: global got snoop WriteReq 
[80a70800:80a70803] UC where needsWritable, does not match isInvalidateMemory 
Usage: 9072952 KBytesProgram aborted at tick 175141645000--- BEGIN LIBC 
BACKTRACE ---At the moment the project uses classic caches. Private L1 and 
shared L2 caches. I didn't test it with L3 caches as the simulation crashes 
sometimes.Is it possible that the error occurs because of the classic caches 
and cache coherence?Might the error vanish when using Ruby? An L3 cache should 
also be implemented. Is it difficult to do that in Ruby?
Thank you very much for your help.
Best regardsSebastian
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[gem5-users] Re: Reading from memory in Gem5

[Jason Lowe-Power via gem5-users]

Hello,

Is this a debug-only read or are you trying to simulate the timing for the
read? Do you want to see what's in the main memory or do you want to see
the up-to-date values in the caches? The answers to these questions will
drive what type of access you want to make and what object you want to use
to make the access.

Generally, you can simply construct a packet and send a request of any size
to any object. See
http://www.gem5.org/documentation/learning_gem5/part2/simplecache/ for
details on how to send/receive memory requests.

Cheers,
Jason

PS: There is no need to send multiple emails. People will either respond or
they won't. Spamming the list (and individuals) will *decrease* the chance
of a response due to causing people to get frustrated. Please don't stop
asking questions! But it's important to be polite when asking them :).

On Thu, Aug 6, 2020 at 12:44 PM ABD ALRHMAN ABO ALKHEEL <
abdkeel...@hotmail.com> wrote:

> Hi Jason,
>
> I want to clarify what I want to do; I want to run a program on gem5 (in
> SE mode) for 1M instructions and I want to save the memory addresses that
> every LD instruction loads data from ( I can get those addresses from the
> pushRequest method in the lsq)
> http://doxygen.gem5.org/release/current/classLSQ.html and saving those
> addresses in a table (map). After a specific time for example (every100k
> instructions), I want to access the memory to read the data from those
> addresses. For instance, let us assume that the address that load
> instruction loads data from it is (0x78226e68), can I read the content
> of this memory address? Also can I read the 256 bytes of this address (
> 0x78226e00-0x78226eff)? If so, how?
>
> Thanks
>
>
> --
> *From:* Jason Lowe-Power 
> *Sent:* Tuesday, August 4, 2020 4:41 PM
> *To:* ABD ALRHMAN ABO ALKHEEL ; gem5 users
> mailing list 
> *Subject:* Re: [gem5-users] Re: Reading from memory in Gem5
>
> Hello,
>
> First of all, please reply to the users list, not directly to the person
> who responded. This allows everyone to see answers and/or chime in and help.
>
> Second, the page you linked is out of date. Please use the main gem5
> website for all of the up to date documentation (e.g.,
> http://doxygen.gem5.org/release/current/classLSQUnit.html)
>
> Third, I still don't fully understand what your goals are. However, you
> can use the system port (actually, I think I was wrong before, you should
> use the "getPort" function, not "getSystemPort") to make functional (or
> debug) accesses to the memory. You can create a `Packet` with a `Request`
> and send a functional request across the port (i.e., call
> sendFunctional(pkt)). You can use either virtual (in SE mode) or physical
> address (in both modes). I am sure there are some caveats to using virtual
> addresses, but I don't know exactly what they are.
>
> If you're trying to make new timing accesses, then you should use the main
> "dcache_port" and "icache_port" that are connected to the CPU. Again, you
> can construct a Packet object with a Request and send it across the port
> (e.g., sendTimingReq(pkt)).
>
> You may want to read up on the details of how gem5's memory objects work:
> http://www.gem5.org/documentation/learning_gem5/part2/memoryobject/
>
> Cheers,
> Jason
>
>
>
> On Mon, Aug 3, 2020 at 1:15 PM ABD ALRHMAN ABO ALKHEEL <
> abdkeel...@hotmail.com> wrote:
>
> Hi Jason,
>
> Thanks for your email.
>
> What I want to do is finding the memory address that the LD instruction
> loads data from ( I can get the physical and virtual address from the Read
> method in the lsqunit)
> http://pages.cs.wisc.edu/~swilson/gem5-docs/classLSQUnit.html and saving
> those addresses. After a specific time, I want to access the memory to read
> the data from those addresses. Can I use getSystemPort function to access
> the memory and read the data from those addresses? If so, should I use the
> virtual address or the physical address?
>
> Thanks
>
>
> --
> *From:* Jason Lowe-Power 
> *Sent:* Monday, August 3, 2020 3:26 PM
> *To:* gem5 users mailing list 
> *Cc:* gem5-users ; ABD ALRHMAN ABO ALKHEEL <
> abdkeel...@hotmail.com>
> *Subject:* Re: [gem5-users] Re: Reading from memory in Gem5
>
> Hello,
>
> This sounds like you probably want to use "functional" accesses. These are
> built for introspection and debugging, which is what it sounds like you
> want to do. Using the System object, there is a `getSystemPort`
> function that will return a gem5 port that you can use with functional
> accesses to "backdoor" into the memory. See
> http://doxygen.gem5.org/release/current/classSystem.html#a5ecbd1eaa3e0d19f4640bb71a0b59d64
> .
>
> Cheers,
> Jason
>
> On Sun, Aug 2, 2020 at 7:01 AM ABD ALRHMAN ABO ALKHEEL via gem5-users <
> gem5-users@gem5.org> wrote:
>
> Hi All, how to read data from memory in Gem5 ? Can I read data from memory
> in Gem5  for a specific addresses? If so, should I use the virtual address
> or physical address? 

[gem5-users] Re: Error only occurs with higher number of clusters and cpus

[Ciro Santilli via gem5-users]

It might be the same as: https://gem5.atlassian.net/browse/GEM5-711 I want to 
investigate that soon hopefully.

If you try Ruby and it fails, please open a separate bug, we want it to work as 
well 

From: Sebastian Block via gem5-users 
Sent: Friday, August 7, 2020 9:27 AM
To: gem5-users@gem5.org 
Cc: Sebastian Block 
Subject: [gem5-users] Error only occurs with higher number of clusters and cpus

Hi all,

My gem5 project consists of clusters and some cpus in the clusters, simulating 
them in fs mode.
Simulating in atomic mode always works.
While simulating less then 6 cpus works perfectly fine in timing mode, with 
more then 6 the simulation crashes with the error:

panic: panic condition (pkt->needsWritable() != pkt->isInvalidate()) && 
!pkt->req->isCacheMaintenance() occurred: global got snoop WriteReq 
[80a70800:80a70803] UC where needsWritable, does not match isInvalidate
Memory Usage: 9072952 KBytes
Program aborted at tick 175141645000
--- BEGIN LIBC BACKTRACE ---

At the moment the project uses classic caches. Private L1 and shared L2 caches. 
I didn't test it with L3 caches as the simulation crashes sometimes.
Is it possible that the error occurs because of the classic caches and cache 
coherence?
Might the error vanish when using Ruby?
An L3 cache should also be implemented. Is it difficult to do that in Ruby?

Thank you very much for your help.

Best regards
Sebastian

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[gem5-users] Error only occurs with higher number of clusters and cpus

[Sebastian Block via gem5-users]

Hi all,
My gem5 project consists of clusters and some cpus in the clusters, simulating 
them in fs mode.Simulating in atomic mode always works. While simulating less 
then 6 cpus works perfectly fine in timing mode, with more then 6 the 
simulation crashes with the error: 
panic: panic condition (pkt->needsWritable() != pkt->isInvalidate()) && 
!pkt->req->isCacheMaintenance() occurred: global got snoop WriteReq 
[80a70800:80a70803] UC where needsWritable, does not match isInvalidateMemory 
Usage: 9072952 KBytesProgram aborted at tick 175141645000--- BEGIN LIBC 
BACKTRACE ---At the moment the project uses classic caches. Private L1 and 
shared L2 caches. I didn't test it with L3 caches as the simulation crashes 
sometimes.Is it possible that the error occurs because of the classic caches 
and cache coherence?Might the error vanish when using Ruby? An L3 cache should 
also be implemented. Is it difficult to do that in Ruby?
Thank you very much for your help.
Best regardsSebastian
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