[gem5-users] Re: Supplementing experiment Data///答复: How to make scheduleInstStop() function to stop simulate at an accurate expected instructions counts for one core KVM/ATOMIC/O3 CPU simulation?

[Ciro Santilli via gem5-users]

Hi Yichao,

How are you counting the instructions? --debug-flags ExecAll? If so, are you 
excluding pseudo instructions with --debug-flags ExecAll,ExecMicro?

From: Liyichao via gem5-users 
Sent: Monday, August 10, 2020 5:29 AM
To: gem5-users@gem5.org 
Cc: Liyichao 
Subject: [gem5-users] 答复: Supplementing experiment Data///答复: How to make 
scheduleInstStop() function to stop simulate at an accurate expected 
instructions counts for one core KVM/ATOMIC/O3 CPU simulation?


Hi All:

 Are there any experts who can help me to explain the features of the 
scheduleInstStop() function?





李翼超（Charlie）



华为技术有限公司 Huawei Technologies Co., Ltd.

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发件人: Liyichao
发送时间: 2020年8月7日 12:12
收件人: 'gem5-users@gem5.org' 
主题: Supplementing experiment Data///答复: How to make scheduleInstStop() function 
to stop simulate at an accurate expected instructions counts for one core 
KVM/ATOMIC/O3 CPU simulation?







Hi All:



I use the scheduleInstStop() function to let the m5.simulate() stop at a point 
instrutions as my ROI start, for example: 1(100M) instrutions, but when 
the simulate stop, I print the instructions from last start simulation to the 
end, the count always exceed my specified instrutions(100M), like 100423403, 
about 0.4% exceeded. If I set to 137579444 in O3 cpu, when simulation stop, 
totalInsts() print 121264766,about 12% instruction number error.



The more detail the CPU is or the less expected instruction we set to 
scheduleInstStop() , the more error rate the result is.

Can the scheduleInstStop() function to stop simulate at an accurate instrutions 
count?



Below is my experiment data:

SP means each ROI segment number

WT means weight each SP

KVM FF INSTS means expected fastforward instrutions  set to shceduleInstsStop 
in KVM CPU and KVM FF INSTS REAL means actural instructions when simulation 
stopped.

Thes same as DETAIL WARMUP INSTS and DETAIL WARMUP INSTS REAL, ROI START REAL

DETAIL SIM INSTS REAL means actural instructions when simulation stopped.



SP

ROI START INSTS

ROI INSTS

WT

GEM5 CPU time(s)

KVM FF INSTS REAL

KVM FF INSTS

KVM FF ERROR

DETAIL WARMUP INSTS REAL

DETAIL WARMUP INSTS

DETAIL WARMUP ERROR  RATE

ROI START REAL

ROI START ERROR

ROI START ERROR RATE

DETAIL SIM INSTS REAL

ROI ERROR

ROI ERROR RATE

253

10178192697

7961215

0.0831

235.37

10168198363

10168192697

0.56%

11769096

1000

17.69%

10179967459

1774762

0.01744%

9765795

1804580

22.67%

489

14993215251

28956263

0.0807

480.69

14985233613

14983215251

0.013471%

12670891

1000

26.71%

14997904504

4689253

0.03128%

31630388

2674125

9.24%

745

20961513684

7952028

0.0831

366.16

20951519275

20951513684

0.27%

10930605

1000

9.31%

20962449880

936196

0.00447%

9196796

1244768

15.65%

747

20985389544

7913399

0.0831

368.9

20976588014

20975389544

0.005714%

13508368

1000

35.08%

20990096382

4706838

0.02243%

8729639

816240

10.31%

1535

36747557633

71903019

0.0489

852.12

36737563780

36737557633

0.17%

13915280

1000

39.15%

36751479060

3921427

0.01067%

76114831

4211812

5.86%

1576

39801482033

72581100

0.0489

986.37

39791620332

39791482033

0.000348%

13898089

1000

38.98%

39805518421

4036388

0.01014%

76712281

4131181

5.69%

1630

41397216547

7969257

0.0831

576.6

41387222182

41387216547

0.14%

14108619

1000

41.09%

41401330801

4114254

0.00994%

12213236

4243979

53.25%

1678

41875758899

7945777

0.0831

578.1

41871459914

41865758899

0.013617%

14214926

1000

42.15%

41885674840

9915941

0.02368%

12108036

4162259

52.38%

1884

46344067975

28927369

0.0807

845.82

46334073500

46334067975

0.12%

11344254

1000

13.44%

46345417754

1349779

0.00291%

31850077

2922708

10.10%

1919

47342402174

28905117

0.0807

805.16

47332436420

47332402174

0.72%

12802266

1000

28.02%

47345238686

2836512

0.00599%

31773934

2868817

9.92%

1926

47542229035

28886691

0.0807

787.53

47534320414

47532229035

0.004400%

12709174

1000

27.09%

47547029588

4800553

0.01010%

31731786

2845095

9.85%

[gem5-users] How to find the direction of a packet

[Ahmed, Md Rubel via gem5-users]

Hi,

If I attach a communication monitor between two components (lets say in between 
L2 cache and toL2Bus) to observe the packets exchange between them, is it 
possible to know the direction of each packet? For example which packet is 
coming to the L2 Cache or going from L2 cache. I am observing the packets in 
four public functions below of src/mem/comm_monitor.cc:
bool
recvTimingReq
 
(PacketPtr
 pkt)

bool
recvTimingResp
 
(PacketPtr
 pkt)

void
recvTimingSnoopReq
 
(PacketPtr
 pkt)

bool
recvTimingSnoopResp
 
(PacketPtr
 pkt)


Any help is highly appreciated.


Thanks,
Rubel Ahmed

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