Hi gem5's users,
TL;DR:
--
I know that the ARM PMU is partially implemented, thanks to the gem5 source
code and some publications. I have a binary which uses perf_event to access the
PMU on a Linux-based OS, under an ARM processor, on real hardware. Could it use
perf_event inside a gem5 full-system simulation with a Linux kernel, under the
ARM ISA? So far, I haven't found the right way to do it. If someone knows, I
will be very grateful!
Detailed information:
-
I have a binary (developed by myself) which uses perf_event on real ARM
hardware, to get cache misses and mispredicted branches, and it works well. My
"perf_event_attr.type" is configured with "PERF_TYPE_HARDWARE" and the
".config" field with "PERF_COUNT_HW_CACHE_MISSES" and another with
"PERF_COUNT_HW_BRANCH_MISSES." However, when I put this binary on a gem5 fs
simulation, configured with the DerivO3CPU, ArmSystem, and RealView platform, I
got the following error:
"ENOENT (2): No such file or directory"
The perf_event file descriptor is not created by the kernel (equal to -1). I
wish to precise that this error arrives at the return of the perf_event_open()
syscall. Finally, this error is documented in the perf_event_open.2 manpage,
and also discussed here. However, it didn't help me to understand the error
regarding gem5.
I don't know if we can access the PMU through perf_event into gem5. If so,
maybe we have to use RAW events? (i.e., do you know if perf_event is supposed
to be initialized with PERF_EVENT_HARDWARE or PERF_EVENT_RAW, to be used with
gem5?) In the gem5 example code under configs, I have found a snippet in
devices.py which "Instantiates 1 ArmPMU per PE" (addPMUs()). However, after few
tries, I don't understand how to use this correctly and how it is related to
perf_event.
I used a code similar to addPMUs() in devices.py, with PPI interrupts number
20, 21, 22, and 23 (one by core) according to the RealView interrupts mapping,
with the ArmPPI class. However, perf_event_open() still return the same
error. Note also that I got this message during the boot:
src/arch/arm/pmu.cc:293: warn: Not doing anything for write to miscreg
pmuserenr_el0.
This register is documented in the ARMv8-A architecture manual. I have checked
the pmu.cc file, and saw that writing to this register is not implemented (TODO
state). Normally, it should not be a problem since this register allows (when
set to 1) userland access to the PMU, which we don't want because I want to
access it through the Linux kernel perf_event interface.
With --debug-flags=PMUVerbose, I get the following:
0: system.cpu_cluster.cpus0.isa.pmu: Initializing the PMU.
[...]
0: system.cpu_cluster.cpus0.isa.pmu: PMU: Adding Probe Driven event with id
'0x2'as probe system.cpu_cluster.cpus0.itb:Refills
[...]
8687351673751: system.cpu_cluster.cpus0.isa.pmu: Assigning PMU to ContextID 0.
[...]
8687351673751: system.cpu_cluster.cpus0.isa.pmu: updateCounter(31): Disabling
counter
[...]
Now, you know all I know about this issue!
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