[gem5-users] 答复: Re: Ethernet support for ARM FS simulation
Hi Gabe:
I wonder the reason that add a “const” to “code("
${{cls.cxx_type}} create() const;")” in src/python/m5/SimObject.py?
Because the patch modified the src/dev/pci/device.cc, add a
PciBarNoneParams::create() with const:
“PciBarNoneParams::create() const
{
return new PciBarNone(*this);
}”
[cid:image001.png@01D6B5C7.A9C99C90]
李翼超（Charlie）
华为技术有限公司 Huawei Technologies Co., Ltd.
[Company_logo]
部门：计算系统与组件开发部 [云与计算BG]
手 机：15858232899
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地址：中国(China)-杭州(Hangzhou)-滨江区江淑路360号华为杭州研发中心Z4# [3-A06]
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发件人: Gabe Black via gem5-users [mailto:gem5-users@gem5.org]
发送时间: 2020年11月7日 22:42
收件人: gem5 users mailing list
抄送: Gabe Black
主题: [gem5-users] Re: Ethernet support for ARM FS simulation
The way create methods and constructors were set up was standardized and
largely automated recently. If you're backporting a change across when that
happened, you're going to have to adjust those so they work with the old, less
consistent versions, but it should be very straightforward (turning references
into pointers mostly).
Gabe
On Fri, Nov 6, 2020 at 2:53 AM Liyichao
mailto:liyic...@huawei.com>> wrote:
Hi Gabe:
I use your patch to fix my GEM5 20.0.0.3, but somethins wrong in compilation:
[SO PARAM] EtherDevBase -> ARM/params/EtherDevBase.hh
[ CXX] ARM/dev/virtio/pci.cc -> .o
[SO PARAM] EtherDevice -> ARM/params/EtherDevice.hh
[SO PARAM] EtherTap -> ARM/params/EtherTap.hh
[SO PARAM] EtherTapStub -> ARM/params/EtherTapStub.hh
[SO PARAM] DistEtherLink -> ARM/params/DistEtherLink.hh
[SO PARAM] IGbE -> ARM/params/IGbE.hh
[SO PARAM] NSGigE -> ARM/params/NSGigE.hh
[SO PARAM] Sinic -> ARM/params/Sinic.hh
[SO PARAM] IdeController -> ARM/params/IdeController.hh
[SO PARAM] IdeDisk -> ARM/params/IdeDisk.hh
[ENUM STR] ArmPciIntRouting, True -> ARM/enums/ArmPciIntRouting.cc
[ENUM STR] IdeID, True -> ARM/enums/IdeID.cc
[SO PyBind] A9GlobalTimer -> ARM/python/_m5/param_A9GlobalTimer.cc
[SO PyBind] A9SCU -> ARM/python/_m5/param_A9SCU.cc
[SO PyBind] AmbaDmaDevice -> ARM/python/_m5/param_AmbaDmaDevice.cc
[SO PyBind] AmbaFake -> ARM/python/_m5/param_AmbaFake.cc
[SO PyBind] AmbaIntDevice -> ARM/python/_m5/param_AmbaIntDevice.cc
[SO PyBind] AmbaPioDevice -> ARM/python/_m5/param_AmbaPioDevice.cc
[SO PyBind] CopyEngine -> ARM/python/_m5/param_CopyEngine.cc
[SO PyBind] CpuLocalTimer -> ARM/python/_m5/param_CpuLocalTimer.cc
In file included from build/ARM/dev/virtio/pci.hh:43:0,
from build/ARM/dev/virtio/pci.cc:38:
build/ARM/dev/pci/device.hh: In constructor 'PciBar::PciBar(const
PciBarParams&)':
build/ARM/dev/pci/device.hh:74:48: error: no matching function for call to
'SimObject::SimObject(const PciBarParams&)'
PciBar(const PciBarParams ) : SimObject(p) {}
^
In file included from build/ARM/dev/virtio/base.hh:46:0,
from build/ARM/dev/virtio/pci.hh:42,
from build/ARM/dev/virtio/pci.cc:38:
build/ARM/sim/sim_object.hh:120:5: note: candidate: SimObject::SimObject(const
Params*)
SimObject(const Params *_params);
^
build/ARM/sim/sim_object.hh:120:5: note: no known conversion for argument 1
from 'const PciBarParams' to 'const Params* {aka const SimObjectParams*}'
[SO PyBind] DistEtherLink -> ARM/python/_m5/param_DistEtherLink.cc
[SO PyBind] EtherBus -> ARM/python/_m5/param_EtherBus.cc
[SO PyBind] EtherDevBase -> ARM/python/_m5/param_EtherDevBase.cc
[SO PyBind] EtherDevice -> ARM/python/_m5/param_EtherDevice.cc
[SO PyBind] EtherDump -> ARM/python/_m5/param_EtherDump.cc
[SO PyBind] EtherLink -> ARM/python/_m5/param_EtherLink.cc
[SO PyBind] EtherSwitch -> ARM/python/_m5/param_EtherSwitch.cc
[SO PyBind] EtherTap -> ARM/python/_m5/param_EtherTap.cc
[SO PyBind] EtherTapBase -> ARM/python/_m5/param_EtherTapBase.cc
[SO PyBind] EtherTapStub -> ARM/python/_m5/param_EtherTapStub.cc
[SO PyBind] FVPBasePwrCtrl -> ARM/python/_m5/param_FVPBasePwrCtrl.cc
[SO PyBind] GenericArmPciHost -> ARM/python/_m5/param_GenericArmPciHost.cc
[SO PyBind] HDLcd -> ARM/python/_m5/param_HDLcd.cc
[SO PyBind] IGbE -> ARM/python/_m5/param_IGbE.cc
[SO PyBind] IdeController -> ARM/python/_m5/param_IdeController.cc
[SO PyBind] IdeDisk -> ARM/python/_m5/param_IdeDisk.cc
[SO PyBind] NSGigE -> ARM/python/_m5/param_NSGigE.cc
[gem5-users] Re: Ethernet support for ARM FS simulation
The way create methods and constructors were set up was standardized and
largely automated recently. If you're backporting a change across when that
happened, you're going to have to adjust those so they work with the old,
less consistent versions, but it should be very straightforward (turning
references into pointers mostly).
Gabe
On Fri, Nov 6, 2020 at 2:53 AM Liyichao wrote:
> Hi Gabe:
>
> I use your patch to fix my GEM5 20.0.0.3, but somethins wrong in
> compilation:
>
>
>
>
>
> [SO PARAM] EtherDevBase -> ARM/params/EtherDevBase.hh
>
> [ CXX] ARM/dev/virtio/pci.cc -> .o
>
> [SO PARAM] EtherDevice -> ARM/params/EtherDevice.hh
>
> [SO PARAM] EtherTap -> ARM/params/EtherTap.hh
>
> [SO PARAM] EtherTapStub -> ARM/params/EtherTapStub.hh
>
> [SO PARAM] DistEtherLink -> ARM/params/DistEtherLink.hh
>
> [SO PARAM] IGbE -> ARM/params/IGbE.hh
>
> [SO PARAM] NSGigE -> ARM/params/NSGigE.hh
>
> [SO PARAM] Sinic -> ARM/params/Sinic.hh
>
> [SO PARAM] IdeController -> ARM/params/IdeController.hh
>
> [SO PARAM] IdeDisk -> ARM/params/IdeDisk.hh
>
> [ENUM STR] ArmPciIntRouting, True -> ARM/enums/ArmPciIntRouting.cc
>
> [ENUM STR] IdeID, True -> ARM/enums/IdeID.cc
>
> [SO PyBind] A9GlobalTimer -> ARM/python/_m5/param_A9GlobalTimer.cc
>
> [SO PyBind] A9SCU -> ARM/python/_m5/param_A9SCU.cc
>
> [SO PyBind] AmbaDmaDevice -> ARM/python/_m5/param_AmbaDmaDevice.cc
>
> [SO PyBind] AmbaFake -> ARM/python/_m5/param_AmbaFake.cc
>
> [SO PyBind] AmbaIntDevice -> ARM/python/_m5/param_AmbaIntDevice.cc
>
> [SO PyBind] AmbaPioDevice -> ARM/python/_m5/param_AmbaPioDevice.cc
>
> [SO PyBind] CopyEngine -> ARM/python/_m5/param_CopyEngine.cc
>
> [SO PyBind] CpuLocalTimer -> ARM/python/_m5/param_CpuLocalTimer.cc
>
> *In file included from build/ARM/dev/virtio/pci.hh:43:0,*
>
> * from build/ARM/dev/virtio/pci.cc:38:*
>
> *build/ARM/dev/pci/device.hh: In constructor 'PciBar::PciBar(const
> PciBarParams&)':*
>
> *build/ARM/dev/pci/device.hh:74:48: error: no matching function for call
> to 'SimObject::SimObject(const PciBarParams&)'*
>
> * PciBar(const PciBarParams ) : SimObject(p) {}*
>
> *^*
>
> *In file included from build/ARM/dev/virtio/base.hh:46:0,*
>
> * from build/ARM/dev/virtio/pci.hh:42,*
>
> * from build/ARM/dev/virtio/pci.cc:38:*
>
> *build/ARM/sim/sim_object.hh:120:5: note: candidate:
> SimObject::SimObject(const Params*)*
>
> * SimObject(const Params *_params);*
>
> * ^*
>
> *build/ARM/sim/sim_object.hh:120:5: note: no known conversion for
> argument 1 from 'const PciBarParams' to 'const Params* {aka const
> SimObjectParams*}'*
>
> [SO PyBind] DistEtherLink -> ARM/python/_m5/param_DistEtherLink.cc
>
> [SO PyBind] EtherBus -> ARM/python/_m5/param_EtherBus.cc
>
> [SO PyBind] EtherDevBase -> ARM/python/_m5/param_EtherDevBase.cc
>
> [SO PyBind] EtherDevice -> ARM/python/_m5/param_EtherDevice.cc
>
> [SO PyBind] EtherDump -> ARM/python/_m5/param_EtherDump.cc
>
> [SO PyBind] EtherLink -> ARM/python/_m5/param_EtherLink.cc
>
> [SO PyBind] EtherSwitch -> ARM/python/_m5/param_EtherSwitch.cc
>
> [SO PyBind] EtherTap -> ARM/python/_m5/param_EtherTap.cc
>
> [SO PyBind] EtherTapBase -> ARM/python/_m5/param_EtherTapBase.cc
>
> [SO PyBind] EtherTapStub -> ARM/python/_m5/param_EtherTapStub.cc
>
> [SO PyBind] FVPBasePwrCtrl -> ARM/python/_m5/param_FVPBasePwrCtrl.cc
>
> [SO PyBind] GenericArmPciHost -> ARM/python/_m5/param_GenericArmPciHost.cc
>
> [SO PyBind] HDLcd -> ARM/python/_m5/param_HDLcd.cc
>
> [SO PyBind] IGbE -> ARM/python/_m5/param_IGbE.cc
>
> [SO PyBind] IdeController -> ARM/python/_m5/param_IdeController.cc
>
> [SO PyBind] IdeDisk -> ARM/python/_m5/param_IdeDisk.cc
>
> [SO PyBind] NSGigE -> ARM/python/_m5/param_NSGigE.cc
>
> scons: *** [build/ARM/dev/virtio/pci.o] Error 1
>
> scons: building terminated because of errors.
>
> *** Summary of Warnings ***
>
> Warning: Your compiler doesn't support incremental linking and lto at the
> same time, so lto is being disabled. To force lto on anyway, use the
> --force-lto option. That will
>
> disable partial linking.
>
> Warning: While checking protoc version: [Errno 2] No such file or directory
>
> root@ubuntu-kunpeng920-1:/home/l00515693/gem5_repo/gem5# vim
> build/ARM/dev/pci/device.hh
>
> root@ubuntu-kunpeng920-1:/home/l00515693/gem5_repo/gem5# vim
> build/ARM/dev/pci/device.hh
>
>
>
>
>
>
> --
>
> 李翼超（Charlie）
>
>
>
> 华为技术有限公司 Huawei Technologies Co., Ltd.
>
> [image: Company_logo]
>
> 部门：计算系统与组件开发部 [云与计算BG]
>
> 手 机：15858232899
> 电子邮件：liyic...@huawei.com
>
> 地址：中国(China)-杭州(Hangzhou)-滨江区江淑路360号华为杭州研发中心Z4# [3-A06]
> --
>
> 本邮件及其附件含有华为公司的保密信息，仅限于发送给上面地址中列出的个人或群组。禁
> 止任何其他人以任何形式使用（包括但不限于全部或部分地泄露、复制、或散发）本邮件中
> 的信息。如果您错收了本邮件，请您立即电话或邮件通知发件人并删除本邮件！
> This e-mail and its attachments contain confidential information from
> HUAWEI, which
> is intended only for the person or entity whose address is listed above.
> Any
[gem5-users] Re: How to use checkpoint for a specific code in the Gem5 full system mode.
Hi, One way to do it is to use the `--debug-start TICK` option, which will start logging after `TICK` ticks. To figure out the number of simulated ticks, you can run `/sbin/m5` in the guest right before the ROI, then use `m5.curTick()` in the gem5 system config. The output would be useful if the simulation before reaching the ROI is deterministic; but if the simulation is not, the output would provide a somewhat useful estimation. Regards, Hoa Nguyen On 11/6/20, Hasan, S M Shamimul via gem5-users wrote: > Hello. > > I am running the Gem5 in full system mode. I am using the following > command. > > === > build/X86/gem5.opt --debug-flags=DRAM --debug-file=trace.out > configs/example/fs.py --disk-image="/home/cosmogan-image/cosmogan" > --kernel="/home/gem5/pkr_cp/other/vmlinux-4.9.238" > --script="/home/gem5/pkr_cp/other/tmp.sh" > > > My "tmp.sh" file contains the following code. > > #!/bin/sh > /sbin/m5 checkpoint > cd /cosmoGAN/networks > python run_dcgan.py > /sbin/m5 exit > > > The problem is the "trace.out" file that I got contains lots of memory > traces that I do not need (e.g., system boot related memory trace). I need > memory traces for only the following code "python run_dcgan.py." How can I > get it? Please let me know. Thanks a lot in advance. > > Sincerely, > S.M.Shamimul Hasan > > > > ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
