[gem5-users] Re: Extra timing for specific instruction not registered for RISC-V
I just did a quick check, and it looks like the RISCV ISA definition includes support for the instruction based pseudo ops. If you add support to the m5 utility, then it might just work. Gabe On Wed, Dec 2, 2020 at 9:04 PM Volkan Mutlu via gem5-users < gem5-users@gem5.org> wrote: > Hello everyone, I believe I found a small problem with the way custom > timings are handled through the MinorFUTiming class. I wanted to submit it > to the tracker but the Jira webpage constantly keeps refreshing and I can't > access any issue pages. If anybody knows an alternate way to make this > issue known please let me know. > > I was trying to add a new functional unit to the MinorCPU through the > python interface and I specified some custom timings for a set of custom > instructions that I have. One snippet looked like this: > > timings = > [MinorFUTiming(match=0x200300b,mask=0xfe00707f,description='shatransform',extraCommitLat=65,srcRegsRelativeLats=[0]), > > MinorFUTiming(match=0x8000100b,mask=0xfe00707f,description='sipcompress',extraCommitLat=3,srcRegsRelativeLats=[0]), > > MinorFUTiming(match=0x8000200b,mask=0xfe00707f,description='sipfinalize',extraCommitLat=4,srcRegsRelativeLats=[0])] > > But I noticed the extraCommitLat values were not affecting anything in my > simulations. I tracked the issue down to a function called findTiming in > /gem5/src/cpu/minor/func_unit.cc . It seems this is the function > responsible for finding this extra timing information. However, there is a > conditional directive at the beginning of the function that is as follows: > > #if THE_ISA == ARM_ISA > /* This should work for any ISA with a POD mach_inst */ > TheISA::ExtMachInst mach_inst = inst->machInst; > #else > /* Just allow extra decode based on op classes */ > uint64_t mach_inst = 0; > #endif > > So if gem5 is not built for ARM, it seems you can only specify extra > timing information for op classes in general. Different instructions from > the same op class will not get assigned timing information even if you > specify it as I did above. I changed the conditional to be (THE_ISA == > ARM_ISA) || (THE_ISA == RISCV_ISA) , and that seems to have fixed the issue. > > If anybody working with RISC-V builds experienced similar issues maybe > this can help. Also let me know if this fix is somehow not appropriate or > might have other consequences to be mindful of. > > Thanks. > > PS: As an off-topic question, does anyone know of a reliable way to > instrument code running in SE mode for RISC-V? I asked a similar question > here before, m5ops was suggested but there are no m5ops pseudo-instructions > implemented for RISC-V as of now to the best of my knowledge. I've been > trying to make use of hardware performance counters (for instance using > rdcycle), but I find that its unreliable and doesn't add up when compared > to the stat dump that I see from gem5. Thanks in advance. > ___ > gem5-users mailing list -- gem5-users@gem5.org > To unsubscribe send an email to gem5-users-le...@gem5.org > %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s > ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] Extra timing for specific instruction not registered for RISC-V
Hello everyone, I believe I found a small problem with the way custom timings are handled through the MinorFUTiming class. I wanted to submit it to the tracker but the Jira webpage constantly keeps refreshing and I can't access any issue pages. If anybody knows an alternate way to make this issue known please let me know. I was trying to add a new functional unit to the MinorCPU through the python interface and I specified some custom timings for a set of custom instructions that I have. One snippet looked like this: timings = [MinorFUTiming(match=0x200300b,mask=0xfe00707f,description='shatransform',extraCommitLat=65,srcRegsRelativeLats=[0]), MinorFUTiming(match=0x8000100b,mask=0xfe00707f,description='sipcompress',extraCommitLat=3,srcRegsRelativeLats=[0]), MinorFUTiming(match=0x8000200b,mask=0xfe00707f,description='sipfinalize',extraCommitLat=4,srcRegsRelativeLats=[0])] But I noticed the extraCommitLat values were not affecting anything in my simulations. I tracked the issue down to a function called findTiming in /gem5/src/cpu/minor/func_unit.cc . It seems this is the function responsible for finding this extra timing information. However, there is a conditional directive at the beginning of the function that is as follows: #if THE_ISA == ARM_ISA /* This should work for any ISA with a POD mach_inst */ TheISA::ExtMachInst mach_inst = inst->machInst; #else /* Just allow extra decode based on op classes */ uint64_t mach_inst = 0; #endif So if gem5 is not built for ARM, it seems you can only specify extra timing information for op classes in general. Different instructions from the same op class will not get assigned timing information even if you specify it as I did above. I changed the conditional to be (THE_ISA == ARM_ISA) || (THE_ISA == RISCV_ISA) , and that seems to have fixed the issue. If anybody working with RISC-V builds experienced similar issues maybe this can help. Also let me know if this fix is somehow not appropriate or might have other consequences to be mindful of. Thanks. PS: As an off-topic question, does anyone know of a reliable way to instrument code running in SE mode for RISC-V? I asked a similar question here before, m5ops was suggested but there are no m5ops pseudo-instructions implemented for RISC-V as of now to the best of my knowledge. I've been trying to make use of hardware performance counters (for instance using rdcycle), but I find that its unreliable and doesn't add up when compared to the stat dump that I see from gem5. Thanks in advance. ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] Prefetch Accuracy
I want to calculate the prefetch accuracy for stride prefetcher. I saw that there are two variables usefulPrefetches and issuedPrefetches in Base Pefetcher. These are used in Queued Prefetcher class to calculate prefetch accuracy. I tried using them for stride prefetcher as well. But the value of usefulPrefetches is always 0. Is this a bug or am I understanding something wrong? Best Regards, Deepika ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] Re: Preferred way of dumping checkpoints for Aarch64
Boya, thank you for the input. Do you have first hand experience with using the Graviton instances and kvm ? I am also not sure kvm can speedup basic-block collection, but at least it can speedup simpoint collection which is half of the time spent, so that's pretty decent !Best, Arthur Perais TIMA - 46 Avenue Félix Viallet, 38000 GrenobleBureau T419 - Mail d’origine - De: Boya Chen via gem5-users À: gem5-users@gem5.org Cc: chenb...@huawei.com Envoyé: Wed, 02 Dec 2020 09:16:24 +0100 (CET) Objet: [gem5-users] Re: Preferred way of dumping checkpoints for Aarch64 Using KVM mode can be faster. You can use the amazon cloud server with ARM CPU. ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] 答复: Re: Looking for Linux disk image for 64-bit ARM with Ubuntu 18.04 or GLIBC 2.27
Hi： I have use your Ubuntu 18.04 img to bootup, but I want to know how to modify to enable autologin with root and readfile from GEM5, also systemd service work normally. If I cp /init.gem5 to /sbin/init, although it can enable autologin and read script from GEM5,but system can not work. -邮件原件- 发件人: Giacomo Travaglini via gem5-users [mailto:gem5-users@gem5.org] 发送时间: 2020年11月30日 16:47 收件人: gem5 users mailing list 抄送: Giacomo Travaglini 主题: [gem5-users] Re: Looking for Linux disk image for 64-bit ARM with Ubuntu 18.04 or GLIBC 2.27 Hi Jiwon We recently uploaded a prebuilt Ubuntu18.04 on gem5.org: http://dist.gem5.org/dist/current/arm/disks/ubuntu-18.04-arm64-docker.img.bz2 Kind Regards Giacomo > -Original Message- > From: Choe, Jiwon via gem5-users > Sent: 29 November 2020 04:42 > To: gem5 users mailing list > Cc: Choe, Jiwon > Subject: [gem5-users] Looking for Linux disk image for 64-bit ARM with > Ubuntu > 18.04 or GLIBC 2.27 > > Hi all, > > I'm looking for a Linux disk image for 64-bit ARM that has GLIBC > version 2.27 (Ubuntu 18.04+ I think). > > I am trying to run Java JDK that has been compiled on Ubuntu 18.04 > (with GLIBC 2.27) on a gem5 ARM FS simulation. I am currently using > the disk image that I got from here: > http://dist.gem5.org/dist/current/arm/disks/aarch64- > ubuntu-trusty-headless.img.bz2 > > But when I try to run java, I get the following error within the simulated > system: > java -version java -version > > Error: dl failure on line 604 > Error: failed /usr/lib/jvm/jdk/lib/server/libjvm.so, because > /lib/aarch64-linux- > gnu/libm.so.6: version `GLIBC_2.27' not found (required by > /usr/lib/jvm/jdk/lib/server/libjvm.so) > > > I think this happens because the disk image that I am using runs > Ubuntu 14.04, which has GLIBC 2.19, but I compiled the java executable > on Ubuntu 18.04 with GLIBC 2.27. > > So, if anyone has a Linux disk image (for 64-bit ARM) that has GLIBC > 2.27, or if anyone knows how to upgrade GLIBC on the existing disk > image, I would greatly appreciate your help. > > Thanks! > Jiwon IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] Re: 答复: 答复: Re: Looking for Linux disk image for 64-bit ARM with Ubuntu 18.04 or GLIBC 2.27
Don't use -o,loop with mount. That creates another loopback device and then tries to use that, and apparently reuses /dev/loop4. If you look in /dev, there will also be a /dev/loop4p1 (for instance) for each partition. Mount that device instead. Gabe On Wed, Dec 2, 2020 at 12:07 AM Boya Chen via gem5-users < gem5-users@gem5.org> wrote: > This image can work. > The offset of the image is 65536, not 32256 > ___ > gem5-users mailing list -- gem5-users@gem5.org > To unsubscribe send an email to gem5-users-le...@gem5.org > %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s > ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] Re: Preferred way of dumping checkpoints for Aarch64
Using KVM mode can be faster. You can use the amazon cloud server with ARM CPU. ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] Re: 答复: 答复: Re: Looking for Linux disk image for 64-bit ARM with Ubuntu 18.04 or GLIBC 2.27
This image can work. The offset of the image is 65536, not 32256 ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
