[gem5-users] Re: L2 or L3 cache interface

[Jason Lowe-Power via gem5-users]

Hi Fengze,

No, there is no defined interface between different levels of the cache in
Ruby. Ruby is a "black box" in some sense, with input on the CPU side and
output on the memory side. See
https://www.gem5.org/documentation/learning_gem5/part3/MSIintro/ and
https://www.youtube.com/watch?v=XTIrVBb86aM_channel=JasonLowe-Power for
more information.

Cheers,
Jason

On Mon, Oct 25, 2021 at 6:18 AM Fengze Yu via gem5-users <
gem5-users@gem5.org> wrote:

>
> Hi
>
> What is the interface between L1 and L2 cache in Ruby cache coherence
> model? Is there a clear defined interface, similar to the icachePort and
> dcachePort between CPU and memory, between different levels of caches in
> Ruby?
>
>
> Thanks in advance
>
> Fengze Yu
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[gem5-users] L2 or L3 cache interface

[Fengze Yu via gem5-users]

Hi


What is the interface between L1 and L2 cache in Ruby cache coherence model? Is 
there a clear defined interface, similar to the icachePort and dcachePort 
between CPU and memory, between different levels of caches in Ruby?




Thanks in advance


Fengze Yu___
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[gem5-users] Knowing the number of response packets from the stats generated in gem5 v20+

[Aritra Bagchi via gem5-users]

Hi all,

I am using the gem5 version 21. I can find stats such as
*system.cpu.l2..overall_accesses::total* which indicates the
total number of L2 cache accesses of a specific type.

Could anyone tell what stats are in the stats.txt file for knowing a) the
number of responses reaches "membus" from the memory controller (of a
specific type), b) the number of responses reaches from the "membus" to the
LLC (Li-level cache), and so on..in general, the number of responses from
L(i+1) cache to L(i) cache (of a specific type)? Thanks in advance.

Regards,
Aritra
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