[gem5-users] Re: Initialization for memory encription in se mode
Here is an example of the code.
The cache is placed between the CPU and Enc/Dec Engine, and the data size is
adjusted by setting the cacheline to 128 bits.
if(pkt->isWrite()){
unsigned char dec1[16];
for (int i = 0; i < 16; ++i){
dec1[i] = *(pkt->getConstPtr() + i);
}
unsigned char key[16] = {
0x2b, 0x7e, 0x15, 0x16, 0x28, 0xae, 0xd2, 0xa6, 0xab, 0xf7, 0x15,
0x88, 0x09, 0xcf, 0x4f, 0x3c};
unsigned char enc1[16] = {};
AES128_ECB_Encrypt(key, dec1, enc1);
for (int i = 0; i < 16; ++i){
*(pkt->getPtr() + i) = enc1[i];
}
}
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[gem5-users] Initialization for memory encription in se mode
Hello, everyone.
I'm interested in memory encryption.
I am developing a function to encrypt the contents of memory.
I was able to develop a function that reads packet data in SE mode and
encrypts/decrypts it.
We are using getConstPtr() to get the value by incrementing from the address,
and then encrypting and decrypting.
However, we could not develop the initialization part properly, and the
simulation terminates with an unmapped address.
My current idea is to create a "new protected area" by mapping a new virtual
address, encrypt all the existing memory data, copy it to the new area, and
update the packet address every time.
I could not think of a way to implement this method with my skills.
Do you have any good ideas for implementation or a more concise method of
initialization?
Configuration
gem5 version x21.0.1.0
Architecture x86
CPU OoO CPU
I would like to ask about the Enc/Dec Engine in the configuration below.
CPU -> Cache -> Enc/Dec Engine -> MeCtlr - > memory
Log just before exit when ALL is specified as debug flag
173000: system.cache_bus.respLayer0.wrapped_function_event:
EventFunctionWrapped 35 executed @ 173000
173000:
system.cache_bus.cpu_side_port[0]-RespPacketQueue.wrapped_function_event:
EventFunctionWrapped 34 executed @ 173000
173000: system.cpu.icache_port: Received fetch response 0x1008
173000: Event_47: Timing CPU icache tick 47 scheduled @ 173000
173000: Event_47: Timing CPU icache tick 47 executed @ 173000
173000: system.cpu: Complete ICache Fetch for addr 0x1008
173000: system.cpu.[tid:0]: Setting int reg 16 (16) to 0.
173000: global: Getting more bytes.
173000: global: Collecting 8 byte immediate, got 8 bytes.
173000: global: Collected immediate 0x2cd00a1ab1add2e.
173000: global: Calculating the instruction size: basePC: 0x401008 offset: 0x5
origPC: 0x401004 size: 9
173000: global: Decode: Decoded mov instruction:
{
leg = 0,
rex = 0,
vex/xop = 0,
op = {
type = one byte,
op = 0xa0,
},
modRM = 0,
sib = 0,
immediate = 0x2cd00a1ab1add2e,
displacement = 0
dispSize = 0}
173000: system.cpu.[tid:0]: Setting int reg 17 (17) to 0x2cd00a1ab1add2e.
173000: system.cpu: A0 T0 : 0x401004 @_start : mov al
173000: system.cpu: A0 T0 : 0x401004 @_start. 0 : MOV_R_MI : limm t1,
0x2cd00a1ab1add2e : IntAlu : D=0x02cd00a1ab1add2e
flags=(IsInteger|IsMicroop|IsDelayedCommit|IsFirstMicroop)
173000: system.cpu: Fetch
173000: system.cpu: Complete ICache Fetch for addr 0
173000: system.cpu.[tid:0]: Setting int reg 16 (16) to 0.
173000: system.cpu.[tid:0]: Reading int reg 16 (16) as 0.
173000: system.cpu.[tid:0]: Reading int reg 17 (17) as 0x2cd00a1ab1add2e.
173000: global: MOV_R_MI : ld: The address is 0x2cd00a1ab1add2e
173000: system.cpu.mmu.dtb: Translating vaddr 0x2cd00a1ab1add2e.
173000: system.cpu.mmu.dtb: In protected mode.
173000: system.cpu.mmu.dtb: Paging enabled.
173000: system.cpu.mmu.dtb: Handling a TLB miss for address 0x2cd00a1ab1add2e
at pc 0x401004.
173000: system.cpu: A0 T0 : 0x401004 @_start. 1 : MOV_R_MI : ld al,
DS:[t1] : MemRead : A=0x2cd00a1ab1add2e
flags=(IsInteger|IsLoad|IsMicroop|IsLastMicroop)
173000: system.cpu: Fault occured. Handling the fault
panic: Tried to read unmapped address 0x2cd00a1ab1add2e.
PC: 0x401004, Instr: MOV_R_MI : ld al, DS:[t1]
Memory Usage: 1154604 KBytes
Program aborted at tick 173000
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[gem5-users] Re: Run Timed Simulation (Stop After Certain Time)
Hi Prof. Jason, Thanks a lot for your response. The problem is not that we need to set one instruction limit but set one instruction limit, then reset the stats, and then terminate the simulation completely after the "total instruction limit". So, these are basically two termination points; one for warmup and the other for the actual simulation. Thanks. -- *Best,Abdelrahman Hussein* On Mon, Dec 6, 2021 at 8:57 AM Jason Lowe-Power wrote: > Hi Abdelrahman, > > I think you have the right approach. Is the simulation not exiting after > the warmup_inst instructions? > > Cheers, > Jason > > On Sat, Dec 4, 2021 at 11:43 PM Abdelrahman S. Hussein via gem5-users < > gem5-users@gem5.org> wrote: > >> Hello, >> >> I am trying to warm up my gem5 in order to train cache prediction. I am >> doing this by running a timed simulation in order to limit the number of >> instructions executed (if there is a more direction, that would be >> certainly welcomed). >> >> So, how to do this? >> >> I tried the following: >> >> system.setMemCtrl(valid_mem_ctls[args.memory_ctl]) >> system.cpu.max_insts_any_thread = warmup_inst >> >> Also, I tried to set the duration desired for the simulation by passing >> it as an argument to the m5.simulate(). >> >> Thanks. >> >> -- >> >> *Best,Abdelrahman Hussein* >> ___ >> gem5-users mailing list -- gem5-users@gem5.org >> To unsubscribe send an email to gem5-users-le...@gem5.org >> %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s > > ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] Re: Run Timed Simulation (Stop After Certain Time)
Hi Abdelrahman, I think you have the right approach. Is the simulation not exiting after the warmup_inst instructions? Cheers, Jason On Sat, Dec 4, 2021 at 11:43 PM Abdelrahman S. Hussein via gem5-users < gem5-users@gem5.org> wrote: > Hello, > > I am trying to warm up my gem5 in order to train cache prediction. I am > doing this by running a timed simulation in order to limit the number of > instructions executed (if there is a more direction, that would be > certainly welcomed). > > So, how to do this? > > I tried the following: > > system.setMemCtrl(valid_mem_ctls[args.memory_ctl]) > system.cpu.max_insts_any_thread = warmup_inst > > Also, I tried to set the duration desired for the simulation by passing it > as an argument to the m5.simulate(). > > Thanks. > > -- > > *Best,Abdelrahman Hussein* > ___ > gem5-users mailing list -- gem5-users@gem5.org > To unsubscribe send an email to gem5-users-le...@gem5.org > %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
