[gem5-users] Re: Questions about simulating ARM SVE with gem5
Hi Xiaokang. 1. All of those CPU models will be able to execute the same set of instructions since they use the same instruction implementations. The HPI CPU is really just the O3CPU with some of the configuration set a certain way, I think. 2. I don't know for sure, but there are some constants related to it in src/arch/arm/regs/vec.hh. 3. SE mode vs FS mode isn't really related to the benchmark's size, it's more about how much the benchmark or other program depends on the operating system, and how complex its interactions are. Also, SE mode is usually a little simpler to set up since you don't need to build a disk image, get the OS set up, etc, but FS is more realistic since it actually simulates the OS components and hardware. Gabe On Wed, Dec 8, 2021 at 1:54 AM Xiaokang Fan via gem5-users < gem5-users@gem5.org> wrote: > Hi guys, > > I am new to the gem5 simulator. I have a few questions about simulating > ARM SVE using gem5: > > 1. Which cpu model should I use? DerivO3CPU, MinorCPU, O3CPU, HPI? Or > another cpu model? > 2. How do I set the sve vector length? > 3. Which simulation mode should I use if I want to run some large > benchmarks like spec, SE mode or FS mode? > > Thanks a lot! > ___ > gem5-users mailing list -- gem5-users@gem5.org > To unsubscribe send an email to gem5-users-le...@gem5.org > %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] Re: how gem5 loads binaries on SE mode?
Hi Hiromichi, there isn't really any documentation for how that system works. You can find much of the code for it in the src/base/loader directory, and in the Process subclasses for the different architectures in src/arch/. Gabe On Wed, Dec 8, 2021 at 11:47 PM hiromichi.haneda--- via gem5-users < gem5-users@gem5.org> wrote: > Hello, everyone. > > I'm interested in memory encryption. I am interested in memory encryption, > and I came across the problem of memory initialization. I would like to > encrypt the binary in 128 bit units when it is loaded into the memory. > Is there any document on how gem5 loads binaries on SE mode? > > Thank you. > ___ > gem5-users mailing list -- gem5-users@gem5.org > To unsubscribe send an email to gem5-users-le...@gem5.org > %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s > ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] Re: Guest Binaries for X86
Hi James, there are not. I put a little time into making it easier to build your own images with known good configurations and tools, but there's a lot to do there still. Gabe On Wed, Dec 8, 2021 at 10:49 PM jamesbondtia--- via gem5-users < gem5-users@gem5.org> wrote: > Hi, > > I noticed that the gem5 website only has guest binaries for ARM to run in > full system mode, which are up to date and work well. > I wonder if it is possible to have Full System guest Binaries for X86 and > the other architectures. > > Best > > James > ___ > gem5-users mailing list -- gem5-users@gem5.org > To unsubscribe send an email to gem5-users-le...@gem5.org > %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s > ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] Re: ARM Microop vs Macroop
Hi Jason. Some instructions need to be broken down into microops because they might not be realistic to do all at once, or because they need to perform multiple memory accesses. Other instructions don't, so they're implemented as regular instructions which are not broken down into microops. Gabe On Wed, Dec 8, 2021 at 4:22 PM Jason Z via gem5-users wrote: > Hello Everyone, > > I hope you are all doing well! > > I am trying to implement a store instruction in ARM that has Post-index, > Pre-index, and Signed-offset versions, and I'm using a normal store (i.e., > STRX64) as a model to start, but I am running into some confusion with > regard to which versions are microops, macroops, and neither, so I was > wondering if anyone had any clarification on the issue > > I am seeing information about the differences in X86, but I haven't been > able to find anything about it in ARM > > Here is what I've gathered so far: > > STRX64_REG →neither (not IsMicroop/IsMacroop) > STRX64_PRE →IsMacroop (uses microop MicroAddXiUop) > STRX64_POST →IsMacroop (uses microop MicroAddXiUop) > STRX64_IMM→neither (not IsMicroop/IsMacroop) > STRX64_PREAcc →IsMicroop > STRX64_POSTAcc →IsMicroop > > From my understanding, the macroop is broken down into microops, but I am > confused as to why some of the others are listed as microops and some are > listed as neither. If anyone has any insight into how these are different > and how they are used, it would be greatly appreciated > > Thank you for your time! > > Respectfully, > > Jason Z > ___ > gem5-users mailing list -- gem5-users@gem5.org > To unsubscribe send an email to gem5-users-le...@gem5.org > %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] isa functionally implementation
Hi All: I wonder if the semantics of ISA are already implemented in GEM5, but whether it actually implements its functionality in the architecture. For example, the armv8 instruction "ldnp" is defined in the standard that it initiates a direct load from the memory and will not be allocated in the cache. How do I know whether the ldnp instruction is implemented according to the standard function in gem5? Or does gem5 just implement its instruction semantics and not really implement its functions? Are there any tips or guidance on this? Thank you very much. ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
