[gem5-users] Adding use of an external library
I have an external library that I would like to link with my gem5 build. How do I do that? Also the code I want to compile that will use that library needs to include a particular .h file. How do I work that into the build process? Thanks for tips on how to do this! Regards - Eliot Moss ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] Re: Only one cpu was working in a multicore FS simulation in gem5 v21.1.0.2
Hi, It is possible you are not able to bring up secondary CPUs when booting Linux. I would suggest you to have a look at the dmesg dump to check if there’s a problem. Just in case, please update bootloaders by either recompiling them from source or by downloading them at https://www.gem5.org/documentation/general_docs/fullsystem/guest_binaries Kind Regards Giacomo From: Zhang Li via gem5-users Date: Friday, 17 December 2021 at 12:51 To: gem5-users@gem5.org Cc: Zhang Li Subject: [gem5-users] Only one cpu was working in a multicore FS simulation in gem5 v21.1.0.2 Dear, Recently, I found a strange differences in statistics when I run exactly the same command in gem5 v20.1.0.0 and v21.1.0.2 respectively. In v20.1.0.0, all of the 8 cpus have committed instruction. However, in v21.1.0.2, all cpus except cpu0 have a statistics of 0 instruction committed, it seems that only cpu0 was working. Could I get some clues about this? Best regard! [cid:image001.png@01D7F34B.134B55C0] Here is my command. ./build/ARM/gem5.opt -d fs_results/arm/8cores/test_multicores_Minor configs/example/fs.py \ --cpu-type=MinorCPU --sys-clock=2.2GHz --cpu-clock=2.2GHz --num-cpus=8 \ --caches --l2cache --num-l2caches=2 \ --mem-type=HBM2_2000_4H_1x128 --mem-ranks=1 --mem-channels=8 --mem-size=4GB \ --l1d_size=32kB --l1i_size=32kB --l2_size=2MB --l1d_assoc=2 --l1i_assoc=2 --l2_assoc=16 --cacheline_size=64 \ --disk-image=$M5_PATH/full_system_images/disks/gem5_ubuntu16.img --kernel=$M5_PATH/full_system_images/binaries/vmlinux \ -r 1 --restore-with-cpu=MinorCPU --param='system.realview.gic.gem5_extensions=True' IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] Only one cpu was working in a multicore FS simulation in gem5 v21.1.0.2
Dear, Recently, I found a strange differences in statistics when I run exactly the same command in gem5 v20.1.0.0 and v21.1.0.2 respectively. In v20.1.0.0, all of the 8 cpus have committed instruction. However, in v21.1.0.2, all cpus except cpu0 have a statistics of 0 instruction committed, it seems that only cpu0 was working. Could I get some clues about this? Best regard! [cid:ba9b3de2-3cb0-426a-b982-dffbf31ebd65] Here is my command. ./build/ARM/gem5.opt -d fs_results/arm/8cores/test_multicores_Minor configs/example/fs.py \ --cpu-type=MinorCPU --sys-clock=2.2GHz --cpu-clock=2.2GHz --num-cpus=8 \ --caches --l2cache --num-l2caches=2 \ --mem-type=HBM2_2000_4H_1x128 --mem-ranks=1 --mem-channels=8 --mem-size=4GB \ --l1d_size=32kB --l1i_size=32kB --l2_size=2MB --l1d_assoc=2 --l1i_assoc=2 --l2_assoc=16 --cacheline_size=64 \ --disk-image=$M5_PATH/full_system_images/disks/gem5_ubuntu16.img --kernel=$M5_PATH/full_system_images/binaries/vmlinux \ -r 1 --restore-with-cpu=MinorCPU --param='system.realview.gic.gem5_extensions=True' ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] Re: Deadlock with pthread and DerivO3CPU in SE mode
Sehr geehrte Herren/Frauen, ich bin nicht im Büro und habe keine Internetverbindung. Erwarten Sie, dass sich meine Antwort bis zum 3. Januar verzögert. Mit freundlichen Grüßen, Antonio Dear Sir/Madam, I am out of office with low connection to internet. Expect delays in my answer till 3 January. Best regards, Antonio On Dec 17, 2021, at 11:57, Portero, Antonio via gem5-users wrote: Sehr geehrte Herren/Frauen, ich bin nicht im Büro und habe keine Internetverbindung. Erwarten Sie, dass sich meine Antwort bis zum 3. Januar verzögert. Mit freundlichen Grüßen, Antonio Dear Sir/Madam, I am out of office with low connection to internet. Expect delays in my answer till 3 January. Best regards, Antonio On Dec 16, 2021, at 17:33, Brian Schwedock via gem5-users wrote: Hi Jason, Thanks for the response. I will give full system mode a try. Will x86 + classic cache + multicore work with full system mode? Or do I also need to use, e.g., ruby caches? Thanks, Brian On Thu, Dec 16, 2021 at 9:23 AM Jason Lowe-Power wrote: Hi Brian, A few quick thoughts: 1. x86 + classic cache + multicore is not supported. There is a changeset on gerrit (https://gem5-review.googlesource.com/c/public/gem5/+/52303) which may fix this, but it has not been tested widely. 2. SE mode + pthreads will likely not work in all circumstances. The system calls required for pthreads are complex and we may not have implemented them to perfectly match their behavior on Linux 3. Which leads to this: If you want to investigate multicore performance, I would strongly suggest using full system mode. With gem5-resources (https://resources.gem5.org/) it should be straightforward to set up. See also the new gem5 standard library coming in gem5-21.2 (released next week) as well. Cheers, Jason On Wed, Dec 15, 2021 at 7:28 PM Brian Schwedock via gem5-users wrote: Hi, I'm trying to run a simple multithreaded C++ application in SE mode, but I seem to be getting deadlock when running with DerivO3CPU. TimingSimpleCPU does not deadlock. I'm running on the develop branch without modification. Here is the configuration I'm running: ./build/X86/gem5.opt configs/example/se.py --cmd=/path/to/app --num-cpus=16 --cpu-type=DerivO3CPU --caches --l2cache --l1d_size=64kB --l1i_size=16kB --l2_size=4MB --mem-type=DDR3_1600_8x8 My application spawns 16 pthreads, and the threads perform atomic arithmetic operations and use pthread barriers. From what I can tell, the issue is that on one of the barriers only one or two threads are ever woken up once all threads are ready. When running with the above configuration, the simulation just hangs. When I run with ruby caches, the simulation eventually terminates from the Sequencer panicking on "Possible Deadlock detected." Are pthread barriers not currently supported? I tried using m5threads, but as per this issue (https://github.com/gem5/m5threads/issues/2), I can't compile it with my gcc and kernel versions. I would greatly appreciate any help with this issue. Thanks, Brian ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s Forschungszentrum Juelich GmbH 52425 Juelich Sitz der Gesellschaft: Juelich Eingetragen im Handelsregister des Amtsgerichts Dueren Nr. HR B 3498 Vorsitzender des Aufsichtsrats: MinDir Volker Rieke Geschaeftsfuehrung: Prof. Dr.-Ing. Wolfgang Marquardt (Vorsitzender), Karsten Beneke (stellv. Vorsitzender), Prof. Dr. Astrid Lambrecht, Prof. Dr. Frauke Melchior ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] Re: Initialization for memory encription in se mode
Sehr geehrte Herren/Frauen, ich bin nicht im Büro und habe keine Internetverbindung. Erwarten Sie, dass sich meine Antwort bis zum 3. Januar verzögert. Mit freundlichen Grüßen, Antonio Dear Sir/Madam, I am out of office with low connection to internet. Expect delays in my answer till 3 January. Best regards, Antonio On Dec 8, 2021, at 06:22, hiromichi.haneda--- via gem5-users wrote: I thought about encrypting the memory area where the binary was loaded once. How is the area where the binaries are loaded chosen? Is there a way to encrypt a specific memory area only once? Or any other good initialization ideas? Thank you. ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s Forschungszentrum Juelich GmbH 52425 Juelich Sitz der Gesellschaft: Juelich Eingetragen im Handelsregister des Amtsgerichts Dueren Nr. HR B 3498 Vorsitzender des Aufsichtsrats: MinDir Volker Rieke Geschaeftsfuehrung: Prof. Dr.-Ing. Wolfgang Marquardt (Vorsitzender), Karsten Beneke (stellv. Vorsitzender), Prof. Dr. Astrid Lambrecht, Prof. Dr. Frauke Melchior ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] Re: Deadlock with pthread and DerivO3CPU in SE mode
Sehr geehrte Herren/Frauen, ich bin nicht im Büro und habe keine Internetverbindung. Erwarten Sie, dass sich meine Antwort bis zum 3. Januar verzögert. Mit freundlichen Grüßen, Antonio Dear Sir/Madam, I am out of office with low connection to internet. Expect delays in my answer till 3 January. Best regards, Antonio On Dec 17, 2021, at 11:57, Portero, Antonio via gem5-users wrote: Sehr geehrte Herren/Frauen, ich bin nicht im Büro und habe keine Internetverbindung. Erwarten Sie, dass sich meine Antwort bis zum 3. Januar verzögert. Mit freundlichen Grüßen, Antonio Dear Sir/Madam, I am out of office with low connection to internet. Expect delays in my answer till 3 January. Best regards, Antonio On Dec 16, 2021, at 18:12, Jason Lowe-Power via gem5-users wrote: Hi Brian, You can try the patch linked below if you want x86 + multicore + classic. There is a download button on that page. However, this isn't "officially" supported. Some Ruby protocols have been tested with x86 and multiple cores. The details on the gem5-resources website and/or repo should describe what's been tested. Cheers, Jason On Thu, Dec 16, 2021 at 10:36 AM Brian Schwedock via gem5-users wrote: Hi Jason, Thanks for the response. I will give full system mode a try. Will x86 + classic cache + multicore work with full system mode? Or do I also need to use, e.g., ruby caches? Thanks, Brian On Thu, Dec 16, 2021 at 9:23 AM Jason Lowe-Power wrote: Hi Brian, A few quick thoughts: 1. x86 + classic cache + multicore is not supported. There is a changeset on gerrit (https://gem5-review.googlesource.com/c/public/gem5/+/52303) which may fix this, but it has not been tested widely. 2. SE mode + pthreads will likely not work in all circumstances. The system calls required for pthreads are complex and we may not have implemented them to perfectly match their behavior on Linux 3. Which leads to this: If you want to investigate multicore performance, I would strongly suggest using full system mode. With gem5-resources (https://resources.gem5.org/) it should be straightforward to set up. See also the new gem5 standard library coming in gem5-21.2 (released next week) as well. Cheers, Jason On Wed, Dec 15, 2021 at 7:28 PM Brian Schwedock via gem5-users wrote: Hi, I'm trying to run a simple multithreaded C++ application in SE mode, but I seem to be getting deadlock when running with DerivO3CPU. TimingSimpleCPU does not deadlock. I'm running on the develop branch without modification. Here is the configuration I'm running: ./build/X86/gem5.opt configs/example/se.py --cmd=/path/to/app --num-cpus=16 --cpu-type=DerivO3CPU --caches --l2cache --l1d_size=64kB --l1i_size=16kB --l2_size=4MB --mem-type=DDR3_1600_8x8 My application spawns 16 pthreads, and the threads perform atomic arithmetic operations and use pthread barriers. From what I can tell, the issue is that on one of the barriers only one or two threads are ever woken up once all threads are ready. When running with the above configuration, the simulation just hangs. When I run with ruby caches, the simulation eventually terminates from the Sequencer panicking on "Possible Deadlock detected." Are pthread barriers not currently supported? I tried using m5threads, but as per this issue (https://github.com/gem5/m5threads/issues/2), I can't compile it with my gcc and kernel versions. I would greatly appreciate any help with this issue. Thanks, Brian ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s Forschungszentrum Juelich GmbH 52425 Juelich Sitz der Gesellschaft: Juelich Eingetragen im Handelsregister des Amtsgerichts Dueren Nr. HR B 3498 Vorsitzender des Aufsichtsrats: MinDir Volker Rieke Geschaeftsfuehrung: Prof. Dr.-Ing. Wolfgang Marquardt (Vorsitzender), Karsten Beneke (stellv. Vorsitzender), Prof. Dr. Astrid Lambrecht, Prof. Dr. Frauke Melchior ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web
[gem5-users] Re: Read Clean Request Packets
Sehr geehrte Herren/Frauen, ich bin nicht im Büro und habe keine Internetverbindung. Erwarten Sie, dass sich meine Antwort bis zum 3. Januar verzögert. Mit freundlichen Grüßen, Antonio Dear Sir/Madam, I am out of office with low connection to internet. Expect delays in my answer till 3 January. Best regards, Antonio On Dec 8, 2021, at 10:14, Aritra Bagchi via gem5-users wrote: Hi all, I am observing a lot of ReadCleanReq packets in the classic cache of gem5. Could anyone tell me what is the function/significance of these packets? Thanks and regards, Aritra Bagchi Research Scholar, Department of Computer Science and Engineering, Indian Institute of Technology Delhi, New Delhi - 110016 ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s Forschungszentrum Juelich GmbH 52425 Juelich Sitz der Gesellschaft: Juelich Eingetragen im Handelsregister des Amtsgerichts Dueren Nr. HR B 3498 Vorsitzender des Aufsichtsrats: MinDir Volker Rieke Geschaeftsfuehrung: Prof. Dr.-Ing. Wolfgang Marquardt (Vorsitzender), Karsten Beneke (stellv. Vorsitzender), Prof. Dr. Astrid Lambrecht, Prof. Dr. Frauke Melchior ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] Re: ARM Microop vs Macroop
Sehr geehrte Herren/Frauen, ich bin nicht im Büro und habe keine Internetverbindung. Erwarten Sie, dass sich meine Antwort bis zum 3. Januar verzögert. Mit freundlichen Grüßen, Antonio Dear Sir/Madam, I am out of office with low connection to internet. Expect delays in my answer till 3 January. Best regards, Antonio On Dec 12, 2021, at 06:05, Gabe Black via gem5-users wrote: Hi Jason. Some instructions need to be broken down into microops because they might not be realistic to do all at once, or because they need to perform multiple memory accesses. Other instructions don't, so they're implemented as regular instructions which are not broken down into microops. Gabe On Wed, Dec 8, 2021 at 4:22 PM Jason Z via gem5-users wrote: Hello Everyone, I hope you are all doing well! I am trying to implement a store instruction in ARM that has Post-index, Pre-index, and Signed-offset versions, and I'm using a normal store (i.e., STRX64) as a model to start, but I am running into some confusion with regard to which versions are microops, macroops, and neither, so I was wondering if anyone had any clarification on the issue I am seeing information about the differences in X86, but I haven't been able to find anything about it in ARM Here is what I've gathered so far: STRX64_REG →neither (not IsMicroop/IsMacroop) STRX64_PRE →IsMacroop (uses microop MicroAddXiUop) STRX64_POST →IsMacroop (uses microop MicroAddXiUop) STRX64_IMM→neither (not IsMicroop/IsMacroop) STRX64_PREAcc →IsMicroop STRX64_POSTAcc →IsMicroop From my understanding, the macroop is broken down into microops, but I am confused as to why some of the others are listed as microops and some are listed as neither. If anyone has any insight into how these are different and how they are used, it would be greatly appreciated Thank you for your time! Respectfully, Jason Z ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s Forschungszentrum Juelich GmbH 52425 Juelich Sitz der Gesellschaft: Juelich Eingetragen im Handelsregister des Amtsgerichts Dueren Nr. HR B 3498 Vorsitzender des Aufsichtsrats: MinDir Volker Rieke Geschaeftsfuehrung: Prof. Dr.-Ing. Wolfgang Marquardt (Vorsitzender), Karsten Beneke (stellv. Vorsitzender), Prof. Dr. Astrid Lambrecht, Prof. Dr. Frauke Melchior ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] Re: Guest Binaries for X86
Sehr geehrte Herren/Frauen, ich bin nicht im Büro und habe keine Internetverbindung. Erwarten Sie, dass sich meine Antwort bis zum 3. Januar verzögert. Mit freundlichen Grüßen, Antonio Dear Sir/Madam, I am out of office with low connection to internet. Expect delays in my answer till 3 January. Best regards, Antonio On Dec 12, 2021, at 06:06, Gabe Black via gem5-users wrote: Hi James, there are not. I put a little time into making it easier to build your own images with known good configurations and tools, but there's a lot to do there still. Gabe On Wed, Dec 8, 2021 at 10:49 PM jamesbondtia--- via gem5-users wrote: Hi, I noticed that the gem5 website only has guest binaries for ARM to run in full system mode, which are up to date and work well. I wonder if it is possible to have Full System guest Binaries for X86 and the other architectures. Best James ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s Forschungszentrum Juelich GmbH 52425 Juelich Sitz der Gesellschaft: Juelich Eingetragen im Handelsregister des Amtsgerichts Dueren Nr. HR B 3498 Vorsitzender des Aufsichtsrats: MinDir Volker Rieke Geschaeftsfuehrung: Prof. Dr.-Ing. Wolfgang Marquardt (Vorsitzender), Karsten Beneke (stellv. Vorsitzender), Prof. Dr. Astrid Lambrecht, Prof. Dr. Frauke Melchior ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] Re: how gem5 loads binaries on SE mode?
Sehr geehrte Herren/Frauen, ich bin nicht im Büro und habe keine Internetverbindung. Erwarten Sie, dass sich meine Antwort bis zum 3. Januar verzögert. Mit freundlichen Grüßen, Antonio Dear Sir/Madam, I am out of office with low connection to internet. Expect delays in my answer till 3 January. Best regards, Antonio On Dec 12, 2021, at 06:08, Gabe Black via gem5-users wrote: Hi Hiromichi, there isn't really any documentation for how that system works. You can find much of the code for it in the src/base/loader directory, and in the Process subclasses for the different architectures in src/arch/. Gabe On Wed, Dec 8, 2021 at 11:47 PM hiromichi.haneda--- via gem5-users wrote: Hello, everyone. I'm interested in memory encryption. I am interested in memory encryption, and I came across the problem of memory initialization. I would like to encrypt the binary in 128 bit units when it is loaded into the memory. Is there any document on how gem5 loads binaries on SE mode? Thank you. ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s Forschungszentrum Juelich GmbH 52425 Juelich Sitz der Gesellschaft: Juelich Eingetragen im Handelsregister des Amtsgerichts Dueren Nr. HR B 3498 Vorsitzender des Aufsichtsrats: MinDir Volker Rieke Geschaeftsfuehrung: Prof. Dr.-Ing. Wolfgang Marquardt (Vorsitzender), Karsten Beneke (stellv. Vorsitzender), Prof. Dr. Astrid Lambrecht, Prof. Dr. Frauke Melchior ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] Re: Read Clean Request Packets
Sehr geehrte Herren/Frauen, ich bin nicht im Büro und habe keine Internetverbindung. Erwarten Sie, dass sich meine Antwort bis zum 3. Januar verzögert. Mit freundlichen Grüßen, Antonio Dear Sir/Madam, I am out of office with low connection to internet. Expect delays in my answer till 3 January. Best regards, Antonio On Dec 8, 2021, at 10:50, Gabriel Busnot via gem5-users wrote: Hi Aritra, When a cache access misses, the cache in turns issues a request to next level cache or memory to request the line. Depending on whether the line needs to be read or written and other heuristics and policies, the cache will require from the line it gets back to have certain attributes. Uniqueness (exclusivity) and cleanness (equality with memory content) are the most commonly used attributes. In the case of ReadCleanReq, the missing line is requested to be clean, that is up to date with memory. The line will thus be received as one of shared clean or unique clean. A clean line is typically required when a cache knows it is likely to evict it unmodified (i.e., still in clean state). In gem5, this is assumed when a cache is read-only or (mostly) exclusive. Best, Gabriel ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s Forschungszentrum Juelich GmbH 52425 Juelich Sitz der Gesellschaft: Juelich Eingetragen im Handelsregister des Amtsgerichts Dueren Nr. HR B 3498 Vorsitzender des Aufsichtsrats: MinDir Volker Rieke Geschaeftsfuehrung: Prof. Dr.-Ing. Wolfgang Marquardt (Vorsitzender), Karsten Beneke (stellv. Vorsitzender), Prof. Dr. Astrid Lambrecht, Prof. Dr. Frauke Melchior ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] Re: Questions about simulating ARM SVE with gem5
Sehr geehrte Herren/Frauen, ich bin nicht im Büro und habe keine Internetverbindung. Erwarten Sie, dass sich meine Antwort bis zum 3. Januar verzögert. Mit freundlichen Grüßen, Antonio Dear Sir/Madam, I am out of office with low connection to internet. Expect delays in my answer till 3 January. Best regards, Antonio On Dec 12, 2021, at 06:12, Gabe Black via gem5-users wrote: Hi Xiaokang. 1. All of those CPU models will be able to execute the same set of instructions since they use the same instruction implementations. The HPI CPU is really just the O3CPU with some of the configuration set a certain way, I think. 2. I don't know for sure, but there are some constants related to it in src/arch/arm/regs/vec.hh. 3. SE mode vs FS mode isn't really related to the benchmark's size, it's more about how much the benchmark or other program depends on the operating system, and how complex its interactions are. Also, SE mode is usually a little simpler to set up since you don't need to build a disk image, get the OS set up, etc, but FS is more realistic since it actually simulates the OS components and hardware. Gabe On Wed, Dec 8, 2021 at 1:54 AM Xiaokang Fan via gem5-users wrote: Hi guys, I am new to the gem5 simulator. I have a few questions about simulating ARM SVE using gem5: 1. Which cpu model should I use? DerivO3CPU, MinorCPU, O3CPU, HPI? Or another cpu model? 2. How do I set the sve vector length? 3. Which simulation mode should I use if I want to run some large benchmarks like spec, SE mode or FS mode? Thanks a lot! ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s Forschungszentrum Juelich GmbH 52425 Juelich Sitz der Gesellschaft: Juelich Eingetragen im Handelsregister des Amtsgerichts Dueren Nr. HR B 3498 Vorsitzender des Aufsichtsrats: MinDir Volker Rieke Geschaeftsfuehrung: Prof. Dr.-Ing. Wolfgang Marquardt (Vorsitzender), Karsten Beneke (stellv. Vorsitzender), Prof. Dr. Astrid Lambrecht, Prof. Dr. Frauke Melchior ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] Re: Questions about simulating ARM SVE with gem5
Sehr geehrte Herren/Frauen, ich bin nicht im Büro und habe keine Internetverbindung. Erwarten Sie, dass sich meine Antwort bis zum 3. Januar verzögert. Mit freundlichen Grüßen, Antonio Dear Sir/Madam, I am out of office with low connection to internet. Expect delays in my answer till 3 January. Best regards, Antonio On Dec 8, 2021, at 10:53, Xiaokang Fan via gem5-users wrote: Hi guys, I am new to the gem5 simulator. I have a few questions about simulating ARM SVE using gem5: 1. Which cpu model should I use? DerivO3CPU, MinorCPU, O3CPU, HPI? Or another cpu model? 2. How do I set the sve vector length? 3. Which simulation mode should I use if I want to run some large benchmarks like spec, SE mode or FS mode? Thanks a lot! ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s Forschungszentrum Juelich GmbH 52425 Juelich Sitz der Gesellschaft: Juelich Eingetragen im Handelsregister des Amtsgerichts Dueren Nr. HR B 3498 Vorsitzender des Aufsichtsrats: MinDir Volker Rieke Geschaeftsfuehrung: Prof. Dr.-Ing. Wolfgang Marquardt (Vorsitzender), Karsten Beneke (stellv. Vorsitzender), Prof. Dr. Astrid Lambrecht, Prof. Dr. Frauke Melchior ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] Re: isa functionally implementation
Sehr geehrte Herren/Frauen, ich bin nicht im Büro und habe keine Internetverbindung. Erwarten Sie, dass sich meine Antwort bis zum 3. Januar verzögert. Mit freundlichen Grüßen, Antonio Dear Sir/Madam, I am out of office with low connection to internet. Expect delays in my answer till 3 January. Best regards, Antonio On Dec 11, 2021, at 16:21, Liyichao via gem5-users wrote: Hi All: I wonder if the semantics of ISA are already implemented in GEM5, but whether it actually implements its functionality in the architecture. For example, the armv8 instruction "ldnp" is defined in the standard that it initiates a direct load from the memory and will not be allocated in the cache. How do I know whether the ldnp instruction is implemented according to the standard function in gem5? Or does gem5 just implement its instruction semantics and not really implement its functions? Are there any tips or guidance on this? Thank you very much. ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s Forschungszentrum Juelich GmbH 52425 Juelich Sitz der Gesellschaft: Juelich Eingetragen im Handelsregister des Amtsgerichts Dueren Nr. HR B 3498 Vorsitzender des Aufsichtsrats: MinDir Volker Rieke Geschaeftsfuehrung: Prof. Dr.-Ing. Wolfgang Marquardt (Vorsitzender), Karsten Beneke (stellv. Vorsitzender), Prof. Dr. Astrid Lambrecht, Prof. Dr. Frauke Melchior ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] Re: Feed MemRef&PC Stream from CPU to Cache Replacement Policy
Sehr geehrte Herren/Frauen, ich bin nicht im Büro und habe keine Internetverbindung. Erwarten Sie, dass sich meine Antwort bis zum 3. Januar verzögert. Mit freundlichen Grüßen, Antonio Dear Sir/Madam, I am out of office with low connection to internet. Expect delays in my answer till 3 January. Best regards, Antonio On Dec 13, 2021, at 22:31, Abdelrahman S. Hussein via gem5-users wrote: Hello, I am working on implementing a specific cache replacement policy. This policy basically relies on building/collecting the history of both memory references (load/store addresses). Also, it operates using the associating hashed PC of the load/store instructions themselves. So, code-wise, it requires direct access to these factors. Now, in gem5, the cache replacement policies (by default) inherit ReplaceableEntry class, which has the set and the way information for the new replacement. However, assuming my case where I have a block in the design that expects the stream of the aforementioned data (i.e., memory address and PC), I could not find a way through which my replacement policy may have access to this information. How can I solve this? Thanks! -- Best, Abdelrahman Hussein ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s Forschungszentrum Juelich GmbH 52425 Juelich Sitz der Gesellschaft: Juelich Eingetragen im Handelsregister des Amtsgerichts Dueren Nr. HR B 3498 Vorsitzender des Aufsichtsrats: MinDir Volker Rieke Geschaeftsfuehrung: Prof. Dr.-Ing. Wolfgang Marquardt (Vorsitzender), Karsten Beneke (stellv. Vorsitzender), Prof. Dr. Astrid Lambrecht, Prof. Dr. Frauke Melchior ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] Re: how gem5 loads binaries on SE mode?
Sehr geehrte Herren/Frauen, ich bin nicht im Büro und habe keine Internetverbindung. Erwarten Sie, dass sich meine Antwort bis zum 3. Januar verzögert. Mit freundlichen Grüßen, Antonio Dear Sir/Madam, I am out of office with low connection to internet. Expect delays in my answer till 3 January. Best regards, Antonio On Dec 12, 2021, at 15:01, yaogang via gem5-users wrote: Hi Jason & All I am simulating Spec2006 milc workload on ARM taeget. It hangs on SVC instruction. I.saw this.is supported on the model. What is the normal cause of the hang and any quick start for.debug such issues? Regards Yao 姚刚 YaoGang Mobile: +86-5039842(For Welink,eSpace Calls) Email: yaogan...@hisilicon.com 发件人：Gabe Black via gem5-users 收件人：gem5 users mailing list 抄 送：Gabe Black 时 间：2021-12-12 13:12:28 主 题：[gem5-users] Re: how gem5 loads binaries on SE mode? Hi Hiromichi, there isn't really any documentation for how that system works. You can find much of the code for it in the src/base/loader directory, and in the Process subclasses for the different architectures in src/arch/. Gabe On Wed, Dec 8, 2021 at 11:47 PM hiromichi.haneda--- via gem5-users wrote: Hello, everyone. I'm interested in memory encryption. I am interested in memory encryption, and I came across the problem of memory initialization. I would like to encrypt the binary in 128 bit units when it is loaded into the memory. Is there any document on how gem5 loads binaries on SE mode? Thank you. ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s Forschungszentrum Juelich GmbH 52425 Juelich Sitz der Gesellschaft: Juelich Eingetragen im Handelsregister des Amtsgerichts Dueren Nr. HR B 3498 Vorsitzender des Aufsichtsrats: MinDir Volker Rieke Geschaeftsfuehrung: Prof. Dr.-Ing. Wolfgang Marquardt (Vorsitzender), Karsten Beneke (stellv. Vorsitzender), Prof. Dr. Astrid Lambrecht, Prof. Dr. Frauke Melchior ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] Re: Questions about simulating ARM SVE with gem5
Sehr geehrte Herren/Frauen, ich bin nicht im Büro und habe keine Internetverbindung. Erwarten Sie, dass sich meine Antwort bis zum 3. Januar verzögert. Mit freundlichen Grüßen, Antonio Dear Sir/Madam, I am out of office with low connection to internet. Expect delays in my answer till 3 January. Best regards, Antonio On Dec 13, 2021, at 04:06, Xiaokang Fan via gem5-users wrote: Hi Gabe, Thanks very much for your reply! I got answers to some of my questions. 1. I have tested all the CPU models in the SE mode. And found the following CPU models support sve code: AtomicSimpleCPU, DeriveO3CPU, MinorCPU, NonCachingSimpleCPU, O3CPU, TimingSimpleCPU, O3_ARM_v7a_3, and ex5_big. While the following two models do not support sve code: HPI, ex5_LITTLE. 2. I followed this link https://stackoverflow.com/questions/57692765/how-to-change-the-gem5-arm-sve-vector-length, and set the sve vector length successfully. SE mode: se.py --param 'system.cpu[:].isa[:].sve_vl_se = 2' FS mode: fs.py --param 'system.sve_vl = 2' 3. However, I got some problems simulating 435.gromacs from SPEC CPU 2006 using the FS mode. I downloaded the latest image files (aarch-system-20210904.tar.bz2, ubuntu-18.04-arm64-docker.img.bz2) from this link: https://www.gem5.org/documentation/general_docs/fullsystem/guest_binaries. Then I booted the system up using the following command: ./build/ARM/get5.opt configs/example/fs.py --bootloader=binaries/boot.arm64 --kernel=binaries/vmlinux.arm64 --disk=ubuntu-18.04-arm64-docker.img --cpu-type=DerivO3CPU --mem-size="8GB" --param="system.sve_vl = 2" --caches When I ran 435.gromacs in the simulation, I always got the error: "malloc(): invalid size (unsorted)". Then the program "gromacs" is aborted. No matter what the input is, test/train/ref. Do you have any idea what the problem may be? Thanks very much! Gabe Black 于2021年12月12日周日 13:12写道： Hi Xiaokang. 1. All of those CPU models will be able to execute the same set of instructions since they use the same instruction implementations. The HPI CPU is really just the O3CPU with some of the configuration set a certain way, I think. 2. I don't know for sure, but there are some constants related to it in src/arch/arm/regs/vec.hh. 3. SE mode vs FS mode isn't really related to the benchmark's size, it's more about how much the benchmark or other program depends on the operating system, and how complex its interactions are. Also, SE mode is usually a little simpler to set up since you don't need to build a disk image, get the OS set up, etc, but FS is more realistic since it actually simulates the OS components and hardware. Gabe On Wed, Dec 8, 2021 at 1:54 AM Xiaokang Fan via gem5-users wrote: Hi guys, I am new to the gem5 simulator. I have a few questions about simulating ARM SVE using gem5: 1. Which cpu model should I use? DerivO3CPU, MinorCPU, O3CPU, HPI? Or another cpu model? 2. How do I set the sve vector length? 3. Which simulation mode should I use if I want to run some large benchmarks like spec, SE mode or FS mode? Thanks a lot! ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s Forschungszentrum Juelich GmbH 52425 Juelich Sitz der Gesellschaft: Juelich Eingetragen im Handelsregister des Amtsgerichts Dueren Nr. HR B 3498 Vorsitzender des Aufsichtsrats: MinDir Volker Rieke Geschaeftsfuehrung: Prof. Dr.-Ing. Wolfgang Marquardt (Vorsitzender), Karsten Beneke (stellv. Vorsitzender), Prof. Dr. Astrid Lambrecht, Prof. Dr. Frauke Melchior ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] Re: Problem with checkpoint and restoration in gem5 se mode
Sehr geehrte Herren/Frauen, ich bin nicht im Büro und habe keine Internetverbindung. Erwarten Sie, dass sich meine Antwort bis zum 3. Januar verzögert. Mit freundlichen Grüßen, Antonio Dear Sir/Madam, I am out of office with low connection to internet. Expect delays in my answer till 3 January. Best regards, Antonio On Dec 14, 2021, at 16:14, Jordi Vaquero via gem5-users wrote: Hello Gelin and Giacomo, Recently I was using gem5 in se mode to run some SPEC 2006 runs and I realize there is some checkpoint retrieval problem. In my case it doesn't behave like in Gelin case, but I though that better add it here than create a new thread. Some information, • I am working emulating riscv, I didn't check if this is still happens in other architectures. • This specific test I am using is perlbench test1 from SPEC2006. I created a checkpoint with gem5 and when retrieving it the following error appears, build/RISCV/arch/riscv/faults.cc:b4: panic: Illegal instruction 0x at pc 0x000106c4: Memory Usage: 1214492 KBytes Program aborted at tick 4436647500 --- BEGIN LIBC BACKTRACE --- /data1/home/jvaquero/gem5_orig/build/RISCV/gem5.opt(+0xba15cc)[0x55689b81c5cc] /data1/home/jvaquero/gem5_orig/build/RISCV/gem5.opt(+0xbbb2ba)[0x55689b8362ba] /lib/x86_64-linux-gnu/libpthread.so.0(+0x12980)[0x7f3dac504980] /lib/x86_64-linux-gnu/libc.so.6(gsignal+0xc7)[0x7f3daaae0fb7] /lib/x86_64-linux-gnu/libc.so.6(abort+0x141)[0x7f3daaae2921] /data1/home/jvaquero/gem5_orig/build/RISCV/gem5.opt(+0x1f2a7f)[0x55689ae6da7f] /data1/home/jvaquero/gem5_orig/build/RISCV/gem5.opt(+0xa8ffe7)[0x55689b70afe7] /data1/home/jvaquero/gem5_orig/build/RISCV/gem5.opt(+0xa90190)[0x55689b70b190] /data1/home/jvaquero/gem5_orig/build/RISCV/gem5.opt(+0x95a714)[0x55689b5d5714] /data1/home/jvaquero/gem5_orig/build/RISCV/gem5.opt(+0x95b310)[0x55689b5d6310] /data1/home/jvaquero/gem5_orig/build/RISCV/gem5.opt(+0x95d330)[0x55689b5d8330] /data1/home/jvaquero/gem5_orig/build/RISCV/gem5.opt(+0x95d7a8)[0x55689b5d87a8] /data1/home/jvaquero/gem5_orig/build/RISCV/gem5.opt(+0x96c45b)[0x55689b5e745b] /data1/home/jvaquero/gem5_orig/build/RISCV/gem5.opt(+0xbac815)[0x55689b827815] /data1/home/jvaquero/gem5_orig/build/RISCV/gem5.opt(+0xbdc120)[0x55689b857120] /data1/home/jvaquero/gem5_orig/build/RISCV/gem5.opt(+0xbdca52)[0x55689b857a52] /data1/home/jvaquero/gem5_orig/build/RISCV/gem5.opt(+0xb91a0e)[0x55689b80ca0e] /data1/home/jvaquero/gem5_orig/build/RISCV/gem5.opt(+0x62e965)[0x55689b2a9965] /usr/lib/x86_64-linux-gnu/libpython3.6m.so.1.0(PyCFunction_Call+0x96)[0x7f3dac924736] /usr/lib/x86_64-linux-gnu/libpython3.6m.so.1.0(_PyEval_EvalFrameDefault+0x76e0)[0x7f3dac895b20] /usr/lib/x86_64-linux-gnu/libpython3.6m.so.1.0(+0x17ba0f)[0x7f3dac88ca0f] /usr/lib/x86_64-linux-gnu/libpython3.6m.so.1.0(+0x17c0fc)[0x7f3dac88d0fc] /usr/lib/x86_64-linux-gnu/libpython3.6m.so.1.0(_PyEval_EvalFrameDefault+0x4ec3)[0x7f3dac893303] /usr/lib/x86_64-linux-gnu/libpython3.6m.so.1.0(+0x17a803)[0x7f3dac88b803] /usr/lib/x86_64-linux-gnu/libpython3.6m.so.1.0(+0x17c2be)[0x7f3dac88d2be] /usr/lib/x86_64-linux-gnu/libpython3.6m.so.1.0(_PyEval_EvalFrameDefault+0x4ec3)[0x7f3dac893303] /usr/lib/x86_64-linux-gnu/libpython3.6m.so.1.0(+0x17ba0f)[0x7f3dac88ca0f] /usr/lib/x86_64-linux-gnu/libpython3.6m.so.1.0(+0x17c0fc)[0x7f3dac88d0fc] /usr/lib/x86_64-linux-gnu/libpython3.6m.so.1.0(_PyEval_EvalFrameDefault+0x4ec3)[0x7f3dac893303] /usr/lib/x86_64-linux-gnu/libpython3.6m.so.1.0(+0x17ba0f)[0x7f3dac88ca0f] /usr/lib/x86_64-linux-gnu/libpython3.6m.so.1.0(PyEval_EvalCodeEx+0x3e)[0x7f3dac88d4ce] /usr/lib/x86_64-linux-gnu/libpython3.6m.so.1.0(PyEval_EvalCode+0x1b)[0x7f3dac88e24b] --- END LIBC BACKTRACE --- Aborted (core dumped) This occurs in gem5.opt as well as in gem5.debug. After some debug and tracing, comparing the full execution and the restored one, I found the main difference is in the following piece of trace 394631500: system.switch_cpus: A0 T0 : 0x62ee2 @Perl_yyparse+408: lh s3, -1720(a4) : MemRead : D=0x A=0x1362d0 FetchSeq=289047 CPSeq=255916 flags=(IsInteger|IsLoad) 394631500: system.switch_cpus: A0 T0 : 0x62ee6 @Perl_yyparse+412: c_li a4, 1 : IntAlu : D=0x0001 FetchSeq=289048 CPSeq=255917 flags=(IsInteger) 394632000: system.switch_cpus: A0 T0 : 0x62ee8 @Perl_yyparse+414: addi a3, zero, 197 : IntAlu : D=0x00c5 FetchSeq=289049 CPSeq=255918 flags=(IsInteger) 394632000: system.switch_cpus: A0 T0 : 0x62eec @Perl_yyparse+418: subw a4, a4, s3: IntAlu : D=0x0001 FetchSeq=289050 CPSeq=255919 flags=(IsInteger) 394632500: system.switch_cpus: A0 T0 : 0x62ef0 @Perl_yyparse+422: c_slli a4, 3 : IntAlu : D=0x0008 FetchSeq=289051 CPSeq=255920 flags=(IsInteger) 394633000: system.switch_cpus: A0 T0 : 0x62ef2 @Perl_yyparse+424: c_add a4, s7 : IntAlu : D=0x001ae5d8 FetchSeq=289
[gem5-users] Re: how gem5 loads binaries on SE mode?
Sehr geehrte Herren/Frauen, ich bin nicht im Büro und habe keine Internetverbindung. Erwarten Sie, dass sich meine Antwort bis zum 3. Januar verzögert. Mit freundlichen Grüßen, Antonio Dear Sir/Madam, I am out of office with low connection to internet. Expect delays in my answer till 3 January. Best regards, Antonio On Dec 14, 2021, at 14:56, hiromichi.haneda--- via gem5-users wrote: Thank you, Gabe. I'll have a good read of src/base/loader and src/arch/X86. One more question, do you know of any way to rewrite the memory contents directly? It seems to take a long time to load the loader and X86, so I would like to know another way as a backup. ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s Forschungszentrum Juelich GmbH 52425 Juelich Sitz der Gesellschaft: Juelich Eingetragen im Handelsregister des Amtsgerichts Dueren Nr. HR B 3498 Vorsitzender des Aufsichtsrats: MinDir Volker Rieke Geschaeftsfuehrung: Prof. Dr.-Ing. Wolfgang Marquardt (Vorsitzender), Karsten Beneke (stellv. Vorsitzender), Prof. Dr. Astrid Lambrecht, Prof. Dr. Frauke Melchior ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] Re: Deadlock with pthread and DerivO3CPU in SE mode
Sehr geehrte Herren/Frauen, ich bin nicht im Büro und habe keine Internetverbindung. Erwarten Sie, dass sich meine Antwort bis zum 3. Januar verzögert. Mit freundlichen Grüßen, Antonio Dear Sir/Madam, I am out of office with low connection to internet. Expect delays in my answer till 3 January. Best regards, Antonio On Dec 16, 2021, at 15:22, Jason Lowe-Power via gem5-users wrote: Hi Brian, A few quick thoughts: 1. x86 + classic cache + multicore is not supported. There is a changeset on gerrit (https://gem5-review.googlesource.com/c/public/gem5/+/52303) which may fix this, but it has not been tested widely. 2. SE mode + pthreads will likely not work in all circumstances. The system calls required for pthreads are complex and we may not have implemented them to perfectly match their behavior on Linux 3. Which leads to this: If you want to investigate multicore performance, I would strongly suggest using full system mode. With gem5-resources (https://resources.gem5.org/) it should be straightforward to set up. See also the new gem5 standard library coming in gem5-21.2 (released next week) as well. Cheers, Jason On Wed, Dec 15, 2021 at 7:28 PM Brian Schwedock via gem5-users wrote: Hi, I'm trying to run a simple multithreaded C++ application in SE mode, but I seem to be getting deadlock when running with DerivO3CPU. TimingSimpleCPU does not deadlock. I'm running on the develop branch without modification. Here is the configuration I'm running: ./build/X86/gem5.opt configs/example/se.py --cmd=/path/to/app --num-cpus=16 --cpu-type=DerivO3CPU --caches --l2cache --l1d_size=64kB --l1i_size=16kB --l2_size=4MB --mem-type=DDR3_1600_8x8 My application spawns 16 pthreads, and the threads perform atomic arithmetic operations and use pthread barriers. From what I can tell, the issue is that on one of the barriers only one or two threads are ever woken up once all threads are ready. When running with the above configuration, the simulation just hangs. When I run with ruby caches, the simulation eventually terminates from the Sequencer panicking on "Possible Deadlock detected." Are pthread barriers not currently supported? I tried using m5threads, but as per this issue (https://github.com/gem5/m5threads/issues/2), I can't compile it with my gcc and kernel versions. I would greatly appreciate any help with this issue. Thanks, Brian ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s Forschungszentrum Juelich GmbH 52425 Juelich Sitz der Gesellschaft: Juelich Eingetragen im Handelsregister des Amtsgerichts Dueren Nr. HR B 3498 Vorsitzender des Aufsichtsrats: MinDir Volker Rieke Geschaeftsfuehrung: Prof. Dr.-Ing. Wolfgang Marquardt (Vorsitzender), Karsten Beneke (stellv. Vorsitzender), Prof. Dr. Astrid Lambrecht, Prof. Dr. Frauke Melchior ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] Re: Deadlock with pthread and DerivO3CPU in SE mode
Sehr geehrte Herren/Frauen, ich bin nicht im Büro und habe keine Internetverbindung. Erwarten Sie, dass sich meine Antwort bis zum 3. Januar verzögert. Mit freundlichen Grüßen, Antonio Dear Sir/Madam, I am out of office with low connection to internet. Expect delays in my answer till 3 January. Best regards, Antonio On Dec 16, 2021, at 02:25, Brian Schwedock via gem5-users wrote: Hi, I'm trying to run a simple multithreaded C++ application in SE mode, but I seem to be getting deadlock when running with DerivO3CPU. TimingSimpleCPU does not deadlock. I'm running on the develop branch without modification. Here is the configuration I'm running: ./build/X86/gem5.opt configs/example/se.py --cmd=/path/to/app --num-cpus=16 --cpu-type=DerivO3CPU --caches --l2cache --l1d_size=64kB --l1i_size=16kB --l2_size=4MB --mem-type=DDR3_1600_8x8 My application spawns 16 pthreads, and the threads perform atomic arithmetic operations and use pthread barriers. From what I can tell, the issue is that on one of the barriers only one or two threads are ever woken up once all threads are ready. When running with the above configuration, the simulation just hangs. When I run with ruby caches, the simulation eventually terminates from the Sequencer panicking on "Possible Deadlock detected." Are pthread barriers not currently supported? I tried using m5threads, but as per this issue (https://github.com/gem5/m5threads/issues/2), I can't compile it with my gcc and kernel versions. I would greatly appreciate any help with this issue. Thanks, Brian ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s Forschungszentrum Juelich GmbH 52425 Juelich Sitz der Gesellschaft: Juelich Eingetragen im Handelsregister des Amtsgerichts Dueren Nr. HR B 3498 Vorsitzender des Aufsichtsrats: MinDir Volker Rieke Geschaeftsfuehrung: Prof. Dr.-Ing. Wolfgang Marquardt (Vorsitzender), Karsten Beneke (stellv. Vorsitzender), Prof. Dr. Astrid Lambrecht, Prof. Dr. Frauke Melchior ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] Re: Deadlock with pthread and DerivO3CPU in SE mode
Sehr geehrte Herren/Frauen, ich bin nicht im Büro und habe keine Internetverbindung. Erwarten Sie, dass sich meine Antwort bis zum 3. Januar verzögert. Mit freundlichen Grüßen, Antonio Dear Sir/Madam, I am out of office with low connection to internet. Expect delays in my answer till 3 January. Best regards, Antonio On Dec 16, 2021, at 17:33, Brian Schwedock via gem5-users wrote: Hi Jason, Thanks for the response. I will give full system mode a try. Will x86 + classic cache + multicore work with full system mode? Or do I also need to use, e.g., ruby caches? Thanks, Brian On Thu, Dec 16, 2021 at 9:23 AM Jason Lowe-Power wrote: Hi Brian, A few quick thoughts: 1. x86 + classic cache + multicore is not supported. There is a changeset on gerrit (https://gem5-review.googlesource.com/c/public/gem5/+/52303) which may fix this, but it has not been tested widely. 2. SE mode + pthreads will likely not work in all circumstances. The system calls required for pthreads are complex and we may not have implemented them to perfectly match their behavior on Linux 3. Which leads to this: If you want to investigate multicore performance, I would strongly suggest using full system mode. With gem5-resources (https://resources.gem5.org/) it should be straightforward to set up. See also the new gem5 standard library coming in gem5-21.2 (released next week) as well. Cheers, Jason On Wed, Dec 15, 2021 at 7:28 PM Brian Schwedock via gem5-users wrote: Hi, I'm trying to run a simple multithreaded C++ application in SE mode, but I seem to be getting deadlock when running with DerivO3CPU. TimingSimpleCPU does not deadlock. I'm running on the develop branch without modification. Here is the configuration I'm running: ./build/X86/gem5.opt configs/example/se.py --cmd=/path/to/app --num-cpus=16 --cpu-type=DerivO3CPU --caches --l2cache --l1d_size=64kB --l1i_size=16kB --l2_size=4MB --mem-type=DDR3_1600_8x8 My application spawns 16 pthreads, and the threads perform atomic arithmetic operations and use pthread barriers. From what I can tell, the issue is that on one of the barriers only one or two threads are ever woken up once all threads are ready. When running with the above configuration, the simulation just hangs. When I run with ruby caches, the simulation eventually terminates from the Sequencer panicking on "Possible Deadlock detected." Are pthread barriers not currently supported? I tried using m5threads, but as per this issue (https://github.com/gem5/m5threads/issues/2), I can't compile it with my gcc and kernel versions. I would greatly appreciate any help with this issue. Thanks, Brian ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s Forschungszentrum Juelich GmbH 52425 Juelich Sitz der Gesellschaft: Juelich Eingetragen im Handelsregister des Amtsgerichts Dueren Nr. HR B 3498 Vorsitzender des Aufsichtsrats: MinDir Volker Rieke Geschaeftsfuehrung: Prof. Dr.-Ing. Wolfgang Marquardt (Vorsitzender), Karsten Beneke (stellv. Vorsitzender), Prof. Dr. Astrid Lambrecht, Prof. Dr. Frauke Melchior ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] Re: Deadlock with pthread and DerivO3CPU in SE mode
Sehr geehrte Herren/Frauen, ich bin nicht im Büro und habe keine Internetverbindung. Erwarten Sie, dass sich meine Antwort bis zum 3. Januar verzögert. Mit freundlichen Grüßen, Antonio Dear Sir/Madam, I am out of office with low connection to internet. Expect delays in my answer till 3 January. Best regards, Antonio On Dec 16, 2021, at 18:12, Jason Lowe-Power via gem5-users wrote: Hi Brian, You can try the patch linked below if you want x86 + multicore + classic. There is a download button on that page. However, this isn't "officially" supported. Some Ruby protocols have been tested with x86 and multiple cores. The details on the gem5-resources website and/or repo should describe what's been tested. Cheers, Jason On Thu, Dec 16, 2021 at 10:36 AM Brian Schwedock via gem5-users wrote: Hi Jason, Thanks for the response. I will give full system mode a try. Will x86 + classic cache + multicore work with full system mode? Or do I also need to use, e.g., ruby caches? Thanks, Brian On Thu, Dec 16, 2021 at 9:23 AM Jason Lowe-Power wrote: Hi Brian, A few quick thoughts: 1. x86 + classic cache + multicore is not supported. There is a changeset on gerrit (https://gem5-review.googlesource.com/c/public/gem5/+/52303) which may fix this, but it has not been tested widely. 2. SE mode + pthreads will likely not work in all circumstances. The system calls required for pthreads are complex and we may not have implemented them to perfectly match their behavior on Linux 3. Which leads to this: If you want to investigate multicore performance, I would strongly suggest using full system mode. With gem5-resources (https://resources.gem5.org/) it should be straightforward to set up. See also the new gem5 standard library coming in gem5-21.2 (released next week) as well. Cheers, Jason On Wed, Dec 15, 2021 at 7:28 PM Brian Schwedock via gem5-users wrote: Hi, I'm trying to run a simple multithreaded C++ application in SE mode, but I seem to be getting deadlock when running with DerivO3CPU. TimingSimpleCPU does not deadlock. I'm running on the develop branch without modification. Here is the configuration I'm running: ./build/X86/gem5.opt configs/example/se.py --cmd=/path/to/app --num-cpus=16 --cpu-type=DerivO3CPU --caches --l2cache --l1d_size=64kB --l1i_size=16kB --l2_size=4MB --mem-type=DDR3_1600_8x8 My application spawns 16 pthreads, and the threads perform atomic arithmetic operations and use pthread barriers. From what I can tell, the issue is that on one of the barriers only one or two threads are ever woken up once all threads are ready. When running with the above configuration, the simulation just hangs. When I run with ruby caches, the simulation eventually terminates from the Sequencer panicking on "Possible Deadlock detected." Are pthread barriers not currently supported? I tried using m5threads, but as per this issue (https://github.com/gem5/m5threads/issues/2), I can't compile it with my gcc and kernel versions. I would greatly appreciate any help with this issue. Thanks, Brian ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s Forschungszentrum Juelich GmbH 52425 Juelich Sitz der Gesellschaft: Juelich Eingetragen im Handelsregister des Amtsgerichts Dueren Nr. HR B 3498 Vorsitzender des Aufsichtsrats: MinDir Volker Rieke Geschaeftsfuehrung: Prof. Dr.-Ing. Wolfgang Marquardt (Vorsitzender), Karsten Beneke (stellv. Vorsitzender), Prof. Dr. Astrid Lambrecht, Prof. Dr. Frauke Melchior ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
