[gem5-users] Re: TraceCPU and ARM ETM
Hi Giacomo, Thanks for the reply. I’m looking to replay both compute instruction delays as well as memory system activity. Essentially have some sort of “X delay” per type of instruction (or some scaled CPI) and then have the memory commands execute as well. Ideally, we’d actually something similar to a cycle accurate model that: 1. Models the real pipeline delay of instructions 2. Recognizes dependencies such that memory operations can correctly stall compute instructions in the trace This is probably not supported by TraceCPU currently I imagine. It’s some hybrid of O3CPU and TraceCPU. From: Giacomo Travaglini Date: Monday, April 25, 2022 at 6:27 AM To: gem5-users@gem5.org Cc: Jonathan Kang Subject: Re: TraceCPU and ARM ETM Hi Jonathan, thanks for your email. I haven't heard of anything like that, but it would be really nice to have an ETM trace player available in gem5. Have you had a look at the TraceCPU documentation available in the gem5 website? [1] The TraceCPU is really supposed to be used for memory-system design explorations, abstracting away the core microarchitecture. Is this what you are looking for? Are you just interested on injecting instruction/data packets, or do you want your trace player to parse and act on a richer set of information? If that is the case, doing an off-line translation from ETM format to elastic trace format might not be what you are looking for. What you could do is to *re-use* part of the TraceCPU code (basically the back-end packet generation) and write your own front-end (ETM parser) and middle logic. Let me know what you think about it. Kind regards, Giacomo From: Jonathan Kang via gem5-users Sent: 13 April 2022 22:17 To: gem5-users@gem5.org Cc: Jonathan Kang Subject: [gem5-users] TraceCPU and ARM ETM Hi all, I’m new to Gem5 (just Googled it) and am interested in TraceCPU. A bit of background on what I’m trying to achieve: 1. I have a device (Snapdragon) that I am capturing ARM ETM traces on. 2. I’m looking for a way to use a trace-driven CPU model to replay these ARM traces in my performance model. 3. Unfortunately, the models from ARM do not support trace-driven; they’re execution-driven only. I’ve read that TraceCPU does consume a trace but that it only supports traces that are generated by O3CPU (with certain timing annotations). I was wondering: has anyone tried converting ETM (possibly with timestamps?) into a format that TraceCPU can consume? Second question: is there documentation that describes the TraceCPU trace format? Perhaps I can write such a tool that’s (decently) accurate. Thanks in advance for any advice! Jonathan. IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] The ARM model simulation is failing when i add "All" debug flag
The terminal contents are as follows: ./build/ARM/gem5.opt --debug-flags=All --debug-file=All_Debug configs/example/se.py --cpu-type=O3CPU --caches -c /home/tom/Documents/gem5/tests/test-progs/hello/bin/arm/linux/hello gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. gem5 version 21.2.1.0 gem5 compiled Mar 25 2022 18:35:14 gem5 started Apr 26 2022 01:31:34 gem5 executing on tom-Latitude-E7450, pid 32261 command line: ./build/ARM/gem5.opt --debug-flags=All --debug-file=All_Debug configs/example/se.py --cpu-type=O3CPU --caches -c /home/tom/Documents/gem5/tests/test-progs/hello/bin/arm/linux/hello Global frequency set at 1 ticks per second warn: No dot file generated. Please install pydot to generate the dot file and pdf. build/ARM/mem/mem_interface.cc:791: warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes) 0: system.remote_gdb: listening for remote gdb on port 7001 REAL SIMULATION build/ARM/sim/simulate.cc:194: info: Entering event queue @ 0. Starting simulation... gem5 has encountered a segmentation fault! --- BEGIN LIBC BACKTRACE --- ./build/ARM/gem5.opt(+0xff96f0)[0x55b3191f16f0] ./build/ARM/gem5.opt(+0x1016795)[0x55b31920e795] /lib/x86_64-linux-gnu/libpthread.so.0(+0x143c0)[0x7fab86bdd3c0] ./build/ARM/gem5.opt(+0xc60ae6)[0x55b318e58ae6] ./build/ARM/gem5.opt(+0xc610df)[0x55b318e590df] ./build/ARM/gem5.opt(+0xc5ad78)[0x55b318e52d78] ./build/ARM/gem5.opt(+0xc5cb26)[0x55b318e54b26] ./build/ARM/gem5.opt(+0xbc6686)[0x55b318dbe686] ./build/ARM/gem5.opt(+0xbcbd85)[0x55b318dc3d85] ./build/ARM/gem5.opt(+0xba20b4)[0x55b318d9a0b4] ./build/ARM/gem5.opt(+0x1005c92)[0x55b3191fdc92] ./build/ARM/gem5.opt(+0x10341b4)[0x55b31922c1b4] ./build/ARM/gem5.opt(+0x1034f0e)[0x55b31922cf0e] ./build/ARM/gem5.opt(+0xcd4d72)[0x55b318eccd72] ./build/ARM/gem5.opt(+0x9262c7)[0x55b318b1e2c7] /lib/x86_64-linux-gnu/libpython3.8.so.1.0(+0x2a8738)[0x7fab86e94738] /lib/x86_64-linux-gnu/libpython3.8.so.1.0(_PyEval_EvalFrameDefault+0x8dd8)[0x7fab86c69f48] /lib/x86_64-linux-gnu/libpython3.8.so.1.0(_PyEval_EvalCodeWithName+0x8fb)[0x7fab86db6e3b] /lib/x86_64-linux-gnu/libpython3.8.so.1.0(_PyFunction_Vectorcall+0x94)[0x7fab86e94114] /lib/x86_64-linux-gnu/libpython3.8.so.1.0(+0x74d6d)[0x7fab86c60d6d] /lib/x86_64-linux-gnu/libpython3.8.so.1.0(_PyEval_EvalFrameDefault+0x7d86)[0x7fab86c68ef6] /lib/x86_64-linux-gnu/libpython3.8.so.1.0(+0x8006b)[0x7fab86c6c06b] /lib/x86_64-linux-gnu/libpython3.8.so.1.0(+0x74d6d)[0x7fab86c60d6d] /lib/x86_64-linux-gnu/libpython3.8.so.1.0(_PyEval_EvalFrameDefault+0x12fd)[0x7fab86c6246d] /lib/x86_64-linux-gnu/libpython3.8.so.1.0(_PyEval_EvalCodeWithName+0x8fb)[0x7fab86db6e3b] /lib/x86_64-linux-gnu/libpython3.8.so.1.0(_PyFunction_Vectorcall+0x94)[0x7fab86e94114] /lib/x86_64-linux-gnu/libpython3.8.so.1.0(+0x74d6d)[0x7fab86c60d6d] /lib/x86_64-linux-gnu/libpython3.8.so.1.0(_PyEval_EvalFrameDefault+0x7d86)[0x7fab86c68ef6] /lib/x86_64-linux-gnu/libpython3.8.so.1.0(_PyEval_EvalCodeWithName+0x8fb)[0x7fab86db6e3b] /lib/x86_64-linux-gnu/libpython3.8.so.1.0(PyEval_EvalCodeEx+0x42)[0x7fab86db71c2] /lib/x86_64-linux-gnu/libpython3.8.so.1.0(PyEval_EvalCode+0x1f)[0x7fab86db75af] /lib/x86_64-linux-gnu/libpython3.8.so.1.0(+0x1cfbf1)[0x7fab86dbbbf1] --- END LIBC BACKTRACE --- Segmentation fault (core dumped) When i specified "Exec" as the debug flag, instead of "All". the simulation got completed without an error. Also, when i tried running "Dhrystone" application on the same O3CPU or minor, the simulation didnt get completed when using "Exec" flag (loop count for dhrystone was only 10). It was as if simulator got stuck. Please let me know if i need to provide any additional information Regards, Tom ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] Re: TraceCPU and ARM ETM
Hi Jonathan, thanks for your email. I haven't heard of anything like that, but it would be really nice to have an ETM trace player available in gem5. Have you had a look at the TraceCPU documentation available in the gem5 website? [1] The TraceCPU is really supposed to be used for memory-system design explorations, abstracting away the core microarchitecture. Is this what you are looking for? Are you just interested on injecting instruction/data packets, or do you want your trace player to parse and act on a richer set of information? If that is the case, doing an off-line translation from ETM format to elastic trace format might not be what you are looking for. What you could do is to *re-use* part of the TraceCPU code (basically the back-end packet generation) and write your own front-end (ETM parser) and middle logic. Let me know what you think about it. Kind regards, Giacomo From: Jonathan Kang via gem5-users Sent: 13 April 2022 22:17 To: gem5-users@gem5.org Cc: Jonathan Kang Subject: [gem5-users] TraceCPU and ARM ETM Hi all, I’m new to Gem5 (just Googled it) and am interested in TraceCPU. A bit of background on what I’m trying to achieve: 1. I have a device (Snapdragon) that I am capturing ARM ETM traces on. 2. I’m looking for a way to use a trace-driven CPU model to replay these ARM traces in my performance model. 3. Unfortunately, the models from ARM do not support trace-driven; they’re execution-driven only. I’ve read that TraceCPU does consume a trace but that it only supports traces that are generated by O3CPU (with certain timing annotations). I was wondering: has anyone tried converting ETM (possibly with timestamps?) into a format that TraceCPU can consume? Second question: is there documentation that describes the TraceCPU trace format? Perhaps I can write such a tool that’s (decently) accurate. Thanks in advance for any advice! Jonathan. IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ___ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
[gem5-users] Re: riscv-ubuntu 20.04 FS mode
Dear Bobby, Thank you very much for your suggestion! Iam able to run the RISCV full image without problems (after 8 hours). The problem was that it requires more than 20GB of RAM in order to complete the process and my machine has only 16GB, as a result the OS killed the process as soon as the RΑΜ + swap was full. I run the gem5 in a server and the process is completed normally. If you create a lighter RISCV gem5-compatible image which requires less RAM and boot time please let me know! :) Best regards, Nikos Quoting Bobby Bruce : Nikos, You shouldn't need to modify this example script at all to use the latest disk image (it'll be downloaded automatically). You should try reverting your changes, recompiling your gem5 (just in case) and try again. It'll take a while, perhaps 7 hours or so to complete. I'd try that to see if it resolves the issue. -- Dr. Bobby R. Bruce Room 3050, Kemper Hall, UC Davis Davis, CA, 95616 web: https://www.bobbybruce.net On Mon, Mar 21, 2022 at 1:31 PM Νικόλαος Ταμπουρατζής < ntampourat...@ece.auth.gr> wrote: I use the following configuration: $GEM5/build/RISCV/gem5.fast -d $GEM5/node0 $GEM5/configs/example/gem5_library/riscv-ubuntu-run.py To be noticed that I have changed the riscv-ubuntu-run.py in order to use your new image as follows: ... image = CustomDiskImageResource( local_path = "$HOME/kernels/disks/riscv-ubuntu.img", disk_root_partition = "1", # This is the partition in the disk image to use. 'None' if there is no disk image ) board.set_kernel_disk_workload( # The RISCV bootloader will be automatically downloaded to the # `~/.cache/gem5` directory if not already present. # The riscv-ubuntu boot-test was tested with riscv-bootloader-5.10 kernel=Resource( "riscv-bootloader-vmlinux-5.10", ), disk_image = image, ) ... Best regards, Nikos Quoting Bobby Bruce : > What configuration script are you using? > > -- > Dr. Bobby R. Bruce > Room 3050, > Kemper Hall, UC Davis > Davis, > CA, 95616 > > web: https://www.bobbybruce.net > > > On Mon, Mar 21, 2022 at 9:50 AM Νικόλαος Ταμπουρατζής via gem5-users < > gem5-users@gem5.org> wrote: > >> Dear Boddy, >> >> Thank you for the image and instructions! However, when I try to >> simulate the image through gem5, after 3 hours the gem5 simulation is >> automatically killed (after the following terminal output) >> >> . >> >> [ OK ] Started Unattended Upgrades Shutdown. >> [ OK ] Started LSB: automatic crash report generation. >> [ OK ] Finished Hold until boot process finishes up. >> [ OK ] Finished Terminate Plymouth Boot Screen. >> [ OK ] Started Serial Getty on hvc0. >> [ OK ] Started Serial Getty on ttyS0. >> Starting Set console scheme... >> >> As a result, the terminal prompt is not shown... >> >> >> To be noticed that the gem5 output is the following: >> >> .. >> build/RISCV/arch/riscv/isa.cc:559: warn: 2647474672536: context 1: >> 17 consecutive SC failures. >> build/RISCV/arch/riscv/isa.cc:559: warn: 2680581940794: context 0: >> 16 consecutive SC failures. >> build/RISCV/arch/riscv/isa.cc:559: warn: 2818816451577: context 1: >> 18 consecutive SC failures. >> Killed >> >> >> Best regards, >> Nikos >> >> >> Quoting Bobby Bruce via gem5-users : >> >> > Hey Nikos, >> > >> > While not any faster, this new disk image, >> > >> http://dist.gem5.org/v21-2/images/riscv/ubuntu-20-04/riscv-ubuntu-20220318.img.gz >> , >> > has been uploaded. We believe it's more stable. The older one >> occasionally >> > didn't boot correctly (at least on our end). This is the same resource, >> so >> > your scripts should continue to work, but now they'll pull this image >> which >> > we believe is more stable. Sorry we took so long getting this live. >> > >> > Kind regards, >> > Bobby >> > -- >> > Dr. Bobby R. Bruce >> > Room 3050, >> > Kemper Hall, UC Davis >> > Davis, >> > CA, 95616 >> > >> > web: https://www.bobbybruce.net >> > >> > >> > On Mon, Mar 14, 2022 at 12:08 PM Νικόλαος Ταμπουρατζής < >> > ntampourat...@ece.auth.gr> wrote: >> > >> >> Dear Boddy, >> >> >> >> I have used the same gem5_init.sh in gem5 X86 architecture and all >> >> systemd services bypassed and it is working properly without READ-ONLY >> >> permissions. So, I believe that it is related either to riscv-image or >> >> gem5 configuration. >> >> >> >> Best regards, >> >> Nikos >> >> >> >> >> >> >> >> Quoting Bobby Bruce : >> >> >> >> > Ok, I just thought about this a bit further, if you skip all the init >> >> > processes in this manner the OS will boot as read-only. This is by >> >> design. >> >> > So while you can pass a script here, it can only do read-only things. >> >> Your >> >> > choices are either to boot properly (with standard init stuff) or >> accept >> >> > this restriction. >> >> > >> >> > -- >> >> > Dr. Bobby R. Bruce >> >> > Room 3050, >> >> > Kemper Hall, UC Davis >> >> > Davis, >> >> > CA, 95616 >> >> > >> >> > web:
