[gem5-users] Re: Gem5 SE mode with SystemC for RISC-V

[siva sankar via gem5-users]

Hi Zitai,

In config_mem() in configs/common/MemConfig.py, commenting out the
following worked for me:

  if opt_tlm_memory:system.external_memory =
m5.objects.ExternalSlave(port_type="tlm_slave",
port_data=opt_tlm_memory,
port=system.membus.mem_side_ports,
addr_ranges=system.mem_ranges,)
#system.workload.addr_check = False --> workload return

system.workload doesn't have the attribute addr_check

Thanks,

Shankar Gudla


On Fri, Aug 4, 2023 at 11:45 AM Harshil Patel via gem5-users <
gem5-users@gem5.org> wrote:

> Hi Zitai,
>
> Here are  some examples of using SystemC with gem5:
> https://github.com/gem5/gem5/blob/develop/configs/example/dramsys.py
> https://github.com/gem5/gem5/tree/develop/util/tlm
>
> However, it should be noted that the integration of SystemC with gem5 is
> not being actively maintained by the community.
>
> Regards,
> Harshil
>
> On Fri, Aug 4, 2023 at 2:31 AM 泰。 via gem5-users 
> wrote:
>
>>
>> Hello All,
>> I have been searching for a demonstration or example that showcases the
>> integration of Gem5 SE mode with SystemC for the RISC-V architecture.
>>
>> I am a beginner in Gem5, and I am trying to connect using the following
>> method, but I am facing an 'AttributeError: Class StubWorkload has no
>> parameter addr_check' error. I don't know how to resolve it.
>>
>> cd util/tlm
>> ../../build/RISCV/gem5.debug ../../configs/example/se.py\
>> --tlm-memory=transactor \
>> --cpu-type=TimingSimpleCPU  \
>> --num-cpu=1 \
>> --mem-type=SimpleMemory \
>> --mem-size=512MB\
>> --mem-channels=1\
>> --cmd=../../tests/test-progs/hello/bin/riscv/linux/hello\
>> --caches --l2cache
>>
>> Does the thread below have a final conclusion and examples in the current
>> version of Gem5？
>>
>> https://harmonylists.io/empathy/thread/65EU5R5SPC2ESETWHTYPLMGPJBCCMZMY?hash=37CBTLUSQYNZFID73WZMGBB5NNAL5E64#37CBTLUSQYNZFID73WZMGBB5NNAL5E64
>>
>> Best regards,
>> Zitai
>>
>>
>>
>> ___
>> gem5-users mailing list -- gem5-users@gem5.org
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>>
> ___
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-- 
Thanks and regards
Siva Sankar G
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[gem5-users] Re: Gem5 SE mode with SystemC for RISC-V

[Harshil Patel via gem5-users]

Hi Zitai,

Here are  some examples of using SystemC with gem5:
https://github.com/gem5/gem5/blob/develop/configs/example/dramsys.py
https://github.com/gem5/gem5/tree/develop/util/tlm

However, it should be noted that the integration of SystemC with gem5 is
not being actively maintained by the community.

Regards,
Harshil

On Fri, Aug 4, 2023 at 2:31 AM 泰。 via gem5-users 
wrote:

>
> Hello All,
> I have been searching for a demonstration or example that showcases the
> integration of Gem5 SE mode with SystemC for the RISC-V architecture.
>
> I am a beginner in Gem5, and I am trying to connect using the following
> method, but I am facing an 'AttributeError: Class StubWorkload has no
> parameter addr_check' error. I don't know how to resolve it.
>
> cd util/tlm
> ../../build/RISCV/gem5.debug ../../configs/example/se.py\
> --tlm-memory=transactor \
> --cpu-type=TimingSimpleCPU  \
> --num-cpu=1 \
> --mem-type=SimpleMemory \
> --mem-size=512MB\
> --mem-channels=1\
> --cmd=../../tests/test-progs/hello/bin/riscv/linux/hello\
> --caches --l2cache
>
> Does the thread below have a final conclusion and examples in the current
> version of Gem5？
>
> https://harmonylists.io/empathy/thread/65EU5R5SPC2ESETWHTYPLMGPJBCCMZMY?hash=37CBTLUSQYNZFID73WZMGBB5NNAL5E64#37CBTLUSQYNZFID73WZMGBB5NNAL5E64
>
> Best regards,
> Zitai
>
>
>
> ___
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>
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[gem5-users] Re: RISCV Vector Extension in gem5

[Jason Lowe-Power via gem5-users]

Hello,

No, we don't have any explicit documentation on this. I think that the
fault-only-first are the few instructions that are not implemented.

Cheers,
Jason

On Thu, Aug 3, 2023 at 10:25 PM X BJ  wrote:

> Hello,
>
> Thank you very much, it is exactly what I need !
>
> BTW, is there a instruction list that supported ? Because I notice that
> vector load unit-stride fault-only-first is not supported, I'm wondering if
> there is a list/site/doc about instructions and other stuff in RVV 1.0.
> Thanks again !
>
> Best regards
> xbj
>
> --
> *发件人:* Jason Lowe-Power 
> *发送时间:* 2023年8月3日 22:33
> *收件人:* The gem5 Users mailing list 
> *抄送:* 谢 佰杰 
> *主题:* Re: [gem5-users] RISCV Vector Extension in gem5
>
> Hello,
>
> Initial RVV support was just merged today! See
> https://github.com/gem5/gem5/pull/83
>
> On Thu, Aug 3, 2023 at 12:29 AM 谢 佰杰 via gem5-users 
> wrote:
>
> Hi all,
> I found that both rivosInc and RALC888 used to work on  RISC-V Vector
> Extension in gem5, but both of them seem to be busy with other things,
> leaving  gem5-rvv 1.0 undone.
> I'm wondering what is the status/plan about RISCV-V Vector Extension in
> gem5 ?
>
> Thanks + regards
> xbj
>
>
>
>- [GEM5-1212] Add RISC-V vector support (RVV) version 1.0 - Jira
>(atlassian.net) 
>
>
>- RALC88/gem5: This is an read-only mirror of the gem5 simulator. The
>upstream repository is stored in https://gem5.googlesource.com, code
>reviews should be submitted to https://gem5-review.googlesource.com/. The
>mirrors are synchronized every 15 minutes. (github.com)
>
>
>
>
>
>
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>
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[gem5-users] Gem5 SE mode with SystemC for RISC-V

[泰。 via gem5-users]

Hello All,

I have been searching for a demonstration or example that showcases the 
integration of Gem5 SE mode with SystemC for the RISC-V architecture.



I am a beginner in Gem5, and I am trying to connect using the following method, 
but I am facing an 'AttributeError: Class StubWorkload has no parameter 
addr_check' error. I don't know how to resolve it.



cd util/tlm
../../build/RISCV/gem5.debug ../../configs/example/se.py  \
--tlm-memory=transactor 
  \
--cpu-type=TimingSimpleCPU
 \
--num-cpu=1  
   
\
--mem-type=SimpleMemory 
  \
--mem-size=512MB  
   
 \
--mem-channels=1  
   
 \
--cmd=../../tests/test-progs/hello/bin/riscv/linux/hello  \
--caches --l2cache



Does the thread below have a final conclusion and examples in the current 
version of Gem5？

https://harmonylists.io/empathy/thread/65EU5R5SPC2ESETWHTYPLMGPJBCCMZMY?hash=37CBTLUSQYNZFID73WZMGBB5NNAL5E64#37CBTLUSQYNZFID73WZMGBB5NNAL5E64


Best regards,
Zitai___
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