[gem5-users] RV32 support

[Felix Böseler via gem5-users]

Hello everybody,

I know that this question has been already asked but I want to ask again
what the current support for RISC-V in 32bit mode is – particularly for the
FS mode. [1] suggests that no support is implemented currently while [2]
already presented an implementation in 2018. The bit width in the generated
decoder-ns.cc.inc files seem to be fixed for 64bit. The arch of my 32bit
binary seems to be correctly identified as Riscv32 in the fs_workload class
but the execution does not seem to exhibit a 32bit ISA semantic. If RV32 in
FS mode is supported, how do I use it correctly?

Many thanks in advance and best regards,

Felix Böseler

[1] https://gem5.atlassian.net/browse/GEM5-923

[2] Scheffel, Robert (2018): Simulation of RISC-V based Systems in gem5.
Diplomarbeit. Technische Universität Dresden, Dresden.
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[gem5-users] Clarification minor CPU “in-order”

[Felix Böseler via gem5-users]

Hello everybody,

According to [1] the gem5 minor CPU is an in-order processor model and
features a scoreboarding algorithm. However, according to [2] scoreboarding
is a dynamic scheduling algorithm with out-of-order execution like the
Tomasulo algorithm. Therefore, I have the following two questions:

(1) Why is the minor CPU called an in-order CPU model if it has
scoreboarding capabilities? Is it because the issuing happens in-order,
nevertheless?

(2) What is the difference between the O3 CPU model and the minor CPU model
if the minor CPU already has scoreboarding? Does the O3 CPU offers a more
sophisticated dynamic scheduling approach since [3] mentions register
renaming (as in the Tomasulo algorithm).

Many regards and many thanks in advance

Felix Böseler

[1] https://www.gem5.org/documentation/general_docs/cpu_models/minor_cpu

[2] Hennessy, John L.; Patterson, David A. (op. 2012): Computer
architecture. A quantitative approach. 5th ed. Waltham, MA: Morgan
Kaufmann/Elsevier.

[3] https://www.gem5.org/documentation/general_docs/cpu_models/O3CPU
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