[gem5-users] Re: Fail to Boot Multicore Arm System with KVM CPU

2021-04-06 Thread Wenqi Yin via gem5-users 
Hi All,

The problem turns out to be with the recent release v21.0. I rolled back to 
v20.2, it can boot 8+ KVM cpu after applying all the changes discusses before.  

Shall I report this issue anywhere? If so is there any instructions to do so? 
Thanks

Best, 
Wenqi

> On Apr 6, 2021, at 11:54, wq...@utexas.edu wrote:
> 
> Hi Giacomo,
> 
> I pasted the perhaps most relevant dmesg output of guest kernel and the 
> disassembled dtb file snippet (In this case, I use fs_bigLittle.py and boot 4 
> vCPU) . Also attached the full dts and dmesg output in case I left anything.
> 
> [0.00] CPU features: GIC system register CPU interface present but 
> disab
> led by higher exception level
> 
> [0.052000] smp: Bringing up secondary CPUs ...
> [2.004021] random: fast init done
> [2.132023] CPU1: failed to come online
> [2.132023] CPU1: failed in unknown state : 0x0
> [4.244045] CPU2: failed to come online
> [4.244045] CPU2: failed in unknown state : 0x0
> [6.356068] CPU3: failed to come online
> [6.356068] CPU3: failed in unknown state : 0x0
> [8.468091] CPU4: failed to come online
> [8.468091] CPU4: failed in unknown state : 0x0
> [8.468091] smp: Brought up 1 node, 1 CPU
> 
> 
> cpus {
> #address-cells = <0x1>;
> #size-cells = <0x0>;
> 
> cpu@0 {
> device_type = "cpu";
> compatible = "gem5,arm-cpu";
> reg = <0x0>;
> enable-method = "spin-table";
> cpu-release-addr = <0x0 0x87f8>;
> clock-frequency = <0x773593ff>;
> phandle = <0xf>;
> };
> 
> cpu@1 {
> device_type = "cpu";
> compatible = "gem5,arm-cpu";
> reg = <0x1>;
> enable-method = "spin-table";
> cpu-release-addr = <0x0 0x87f8>;
> clock-frequency = <0x773593ff>;
> phandle = <0x10>;
> };
> 
> cpu@2 {
> device_type = "cpu";
> compatible = "gem5,arm-cpu";
> reg = <0x2>;
> enable-method = "spin-table";
> cpu-release-addr = <0x0 0x87f8>;
> clock-frequency = <0x773593ff>;
> phandle = <0x11>;
> };
> 
> cpu@3 {
> device_type = "cpu";
> compatible = "gem5,arm-cpu";
> reg = <0x3>;
> enable-method = "spin-table";
> cpu-release-addr = <0x0 0x87f8>;
> clock-frequency = <0x773593ff>;
> phandle = <0x12>;
> };
> 
> cpu@104 {
> device_type = "cpu";
> compatible = "gem5,arm-cpu";
> reg = <0x104>;
> enable-method = "spin-table";
> cpu-release-addr = <0x0 0x87f8>;
> clock-frequency = <0x3b9ac9ff>;
> phandle = <0x13>;
> };
> };
> 
> best,
> 
> Wenqi
> 
> On 4/6/21 7:35 AM, Giacomo Travaglini wrote:
>> Hi Wenqi,
>> 
>> Could you provide us with the booting log of the guest kernel?
>> 
>> Kind Regards
>> 
>> Giacomo
>> 
>>> -Original Message-
>>> From: Wenqi Yin 
>>> Sent: 06 April 2021 05:48
>>> To: Giacomo Travaglini 
>>> Cc: gem5 users mailing list ; Wenqi Yin
>>> 
>>> Subject: Re: [gem5-users] Fail to Boot Multicore Arm System with KVM CPU
>>> 
>>> Hi Giacomo,
>>> 
>>> Just want to follow up a bit on this, any suggestions on what could be 
>>> causing
>>> the kernel failing to bring up all those secondary CPUs?
>>> 
>>> Best,
>>> Wenqi
 On Apr 1, 2021, at 16:53, Wenqi Yin  wrote:
 
 HI Giacomo,
 
 I add that line of code you pointed me to to the fs_bigLittle.py, now I can
>>> boot into the terminal, however, the kernel cannot bring all but one cpu
>>> online. It’s also a bit strange in the sense that I specify ‘-smp 12’, and 
>>> inside
>>> the guest when I check lscpu, it shows total of 13 CPUs and only cpu0 is
>>> online, cpu1-12 are offline.
 I tried both the stock kernel as well as compiling kernel myself following
>>> your suggestions from earlier email, both have the same issue. Do you have
>>> any suggestions on what could be causing the problem?
 Best,
 Wenqi
 
> On Apr 1, 2021, at 03:28, Giacomo Travaglini
>>>  wrote:
> Yes, apologies, I forgot to mention that.
> As your host is likely using a GICv3 interrupt controller, you need to
>>> entirely emulate the GICv2 and Generic Timer in userspace (gem5).
> This is done via th

[gem5-users] Re: Fail to Boot Multicore Arm System with KVM CPU

2021-04-05 Thread Wenqi Yin via gem5-users 
Hi Giacomo, 

Just want to follow up a bit on this, any suggestions on what could be causing 
the kernel failing to bring up all those secondary CPUs?

Best, 
Wenqi
> On Apr 1, 2021, at 16:53, Wenqi Yin  wrote:
> 
> HI Giacomo, 
> 
> I add that line of code you pointed me to to the fs_bigLittle.py, now I can 
> boot into the terminal, however, the kernel cannot bring all but one cpu 
> online. It’s also a bit strange in the sense that I specify ‘-smp 12’, and 
> inside the guest when I check lscpu, it shows total of 13 CPUs and only cpu0 
> is online, cpu1-12 are offline. 
> 
> I tried both the stock kernel as well as compiling kernel myself following 
> your suggestions from earlier email, both have the same issue. Do you have 
> any suggestions on what could be causing the problem?
> 
> Best, 
> Wenqi
> 
>> On Apr 1, 2021, at 03:28, Giacomo Travaglini  
>> wrote:
>> 
>> Yes, apologies, I forgot to mention that.
>> As your host is likely using a GICv3 interrupt controller, you need to 
>> entirely emulate the GICv2 and Generic Timer in userspace (gem5).
>> 
>> This is done via the simulate_gic (as you have already done) and by removing 
>> the system register interface info from the DTB node
>> 
>> Here's an example:
>> 
>> https://github.com/gem5/gem5/blob/stable/tests/gem5/configs/arm_generic.py#L99
>> 
>> Let me know if this works
>> 
>> Kind Regards
>> 
>> Giacomo
>> 
>> 
>>> -Original Message-
>>> From: wq...@utexas.edu 
>>> Sent: 31 March 2021 19:18
>>> To: Giacomo Travaglini ; gem5 users mailing
>>> list ; wq...@utexas.edu
>>> Subject: Re: [gem5-users] Fail to Boot Multicore Arm System with KVM CPU
>>> 
>>> Hi Giacomo,
>>> 
>>> Thanks for your reply. I tried the solution you suggested, but seems there
>>> are still problems. Just make sure I understood correctly, I specified the
>>> 'machine-type' as 'VExpress_GEM5_V1' and in the VExpress_GEM5_V1_Base
>>> class's definition (src/dev/arm/RealView.py), when instantiating the gic, I 
>>> use:
>>> 
>>> gic = kvm_gicv2_class(dist_addr=0x2c001000, cpu_addr=0x2c002000,
>>>  it_lines=512, gem5_extensions=True)
>>> 
>>> The kvm_gicv2_class will be resolved as MuxingKvmGic, which inherent from
>>> GicV2 class. To make sure the change applied, I also change the default 
>>> value
>>> of gem5_extensions from False to True in the GicV2 class's definition
>>> (src/dev/arm/Gic.py). After rebuild, when starting gem5 there will be a 
>>> panic
>>> says "KVM: failed to create virtual CPU" (from /src/cpu/kvm/vm.cc, when
>>> using ioctl to create vcpu)
>>> 
>>> Another thing I tried is to set the "simulate_gic" of the MuxingKvmGic class
>>> from False to True, this seems help me get around the vCPU creation failure,
>>> however, at some point it faces an assertion failure of:
>>> 
>>> gem5.opt: build/ARM/sim/eventq.hh:763: void
>>> EventQueue::schedule(Event*, Tick, bool): Assertion `when >= getCurTick()'
>>> failed.
>>> Program aborted at tick 112565277000
>>> 
>>> Best,
>>> 
>>> Wenqi
>>> 
>>> On 3/31/21 7:57 AM, Giacomo Travaglini wrote:
 Hi Wenqi,
 
 First of all thanks for the detailed explanation of your problem.
 
> -Original Message-
> From: wqyin--- via gem5-users 
> Sent: 30 March 2021 22:47
> To: gem5-users@gem5.org; wq...@utexas.edu
> Cc: wq...@utexas.edu
> Subject: [gem5-users] Fail to Boot Multicore Arm System with KVM CPU
> 
> Hello all,
> 
> I am trying to model a multicore arm64 system with the
> example/arm/fs_bigLittle.py using kvm cpu. However, when I specify "-
> machine-type VExpress_Gem5_V2_XXX", the kernel panic during booting,
> giving an error message of:
> 
> [0.00] GICv3: Distributor has Range Selector support [
> 0.00]
> GICv3: no VLPI support, direct LPI support [0.00] ITS [mem
> 0x2e01-0x2e02] [0.00] ITS@0x2e01: allocated
> 262144 Devices
> @fc60 (flat, esz 8, psz 64K, shr 1)
> [0.00] ITS@0x2e01: allocated 8192 Interrupt
>>> Collections
> @fc46 (flat, esz 8, psz 64K, shr 1) [0.00] GIC: using LPI 
> property
> table @0xfc47 [0.00] ITS: Allocated 1792 chunks for
>>> LPIs
> [0.00] GICv3: CPU0: found redistributor 0 region
> 0:0x2c01
> [0.00] CPU0: using LPI pending table @0xfc48
>>> [0.00]
> GIC: using cache flushing for LPI property table [0.00] GICv3: 
> GIC:
> unable to set SRE (disabled at EL2), panic ahead [0.00] 
> 
>>> [ cut
> here ] [0.00] kernel BUG at /work/gem5-
> scripts/submodules/linux/arch/arm64/kernel/entry.S:602!
> [0.00] Internal error: Oops - BUG: 0 [#1] PREEMPT SMP [
> 0.00]
> Modules linked in:
> [0.00] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 4.18.0+ #1
> [0.00] Hardware name: V2P-C

[gem5-users] Re: Fail to Boot Multicore Arm System with KVM CPU

2021-04-01 Thread Wenqi Yin via gem5-users 
HI Giacomo, 

I add that line of code you pointed me to to the fs_bigLittle.py, now I can 
boot into the terminal, however, the kernel cannot bring all but one cpu 
online. It’s also a bit strange in the sense that I specify ‘-smp 12’, and 
inside the guest when I check lscpu, it shows total of 13 CPUs and only cpu0 is 
online, cpu1-12 are offline. 

I tried both the stock kernel as well as compiling kernel myself following your 
suggestions from earlier email, both have the same issue. Do you have any 
suggestions on what could be causing the problem?

Best, 
Wenqi

> On Apr 1, 2021, at 03:28, Giacomo Travaglini  
> wrote:
> 
> Yes, apologies, I forgot to mention that.
> As your host is likely using a GICv3 interrupt controller, you need to 
> entirely emulate the GICv2 and Generic Timer in userspace (gem5).
> 
> This is done via the simulate_gic (as you have already done) and by removing 
> the system register interface info from the DTB node
> 
> Here's an example:
> 
> https://github.com/gem5/gem5/blob/stable/tests/gem5/configs/arm_generic.py#L99
> 
> Let me know if this works
> 
> Kind Regards
> 
> Giacomo
> 
> 
>> -Original Message-
>> From: wq...@utexas.edu 
>> Sent: 31 March 2021 19:18
>> To: Giacomo Travaglini ; gem5 users mailing
>> list ; wq...@utexas.edu
>> Subject: Re: [gem5-users] Fail to Boot Multicore Arm System with KVM CPU
>> 
>> Hi Giacomo,
>> 
>> Thanks for your reply. I tried the solution you suggested, but seems there
>> are still problems. Just make sure I understood correctly, I specified the
>> 'machine-type' as 'VExpress_GEM5_V1' and in the VExpress_GEM5_V1_Base
>> class's definition (src/dev/arm/RealView.py), when instantiating the gic, I 
>> use:
>> 
>> gic = kvm_gicv2_class(dist_addr=0x2c001000, cpu_addr=0x2c002000,
>>   it_lines=512, gem5_extensions=True)
>> 
>> The kvm_gicv2_class will be resolved as MuxingKvmGic, which inherent from
>> GicV2 class. To make sure the change applied, I also change the default value
>> of gem5_extensions from False to True in the GicV2 class's definition
>> (src/dev/arm/Gic.py). After rebuild, when starting gem5 there will be a panic
>> says "KVM: failed to create virtual CPU" (from /src/cpu/kvm/vm.cc, when
>> using ioctl to create vcpu)
>> 
>> Another thing I tried is to set the "simulate_gic" of the MuxingKvmGic class
>> from False to True, this seems help me get around the vCPU creation failure,
>> however, at some point it faces an assertion failure of:
>> 
>> gem5.opt: build/ARM/sim/eventq.hh:763: void
>> EventQueue::schedule(Event*, Tick, bool): Assertion `when >= getCurTick()'
>> failed.
>> Program aborted at tick 112565277000
>> 
>> Best,
>> 
>> Wenqi
>> 
>> On 3/31/21 7:57 AM, Giacomo Travaglini wrote:
>>> Hi Wenqi,
>>> 
>>> First of all thanks for the detailed explanation of your problem.
>>> 
 -Original Message-
 From: wqyin--- via gem5-users 
 Sent: 30 March 2021 22:47
 To: gem5-users@gem5.org; wq...@utexas.edu
 Cc: wq...@utexas.edu
 Subject: [gem5-users] Fail to Boot Multicore Arm System with KVM CPU
 
 Hello all,
 
 I am trying to model a multicore arm64 system with the
 example/arm/fs_bigLittle.py using kvm cpu. However, when I specify "-
 machine-type VExpress_Gem5_V2_XXX", the kernel panic during booting,
 giving an error message of:
 
 [0.00] GICv3: Distributor has Range Selector support [0.00]
 GICv3: no VLPI support, direct LPI support [0.00] ITS [mem
 0x2e01-0x2e02] [0.00] ITS@0x2e01: allocated
 262144 Devices
 @fc60 (flat, esz 8, psz 64K, shr 1)
 [0.00] ITS@0x2e01: allocated 8192 Interrupt
>> Collections
 @fc46 (flat, esz 8, psz 64K, shr 1) [0.00] GIC: using LPI 
 property
 table @0xfc47 [0.00] ITS: Allocated 1792 chunks for
>> LPIs
 [0.00] GICv3: CPU0: found redistributor 0 region
 0:0x2c01
 [0.00] CPU0: using LPI pending table @0xfc48
>> [0.00]
 GIC: using cache flushing for LPI property table [0.00] GICv3: GIC:
 unable to set SRE (disabled at EL2), panic ahead [0.00] 
 
>> [ cut
 here ] [0.00] kernel BUG at /work/gem5-
 scripts/submodules/linux/arch/arm64/kernel/entry.S:602!
 [0.00] Internal error: Oops - BUG: 0 [#1] PREEMPT SMP [
 0.00]
 Modules linked in:
 [0.00] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 4.18.0+ #1
 [0.00] Hardware name: V2P-CA15 (DT) [0.00] pstate:
>> 8085
 (Nzcv daIf -PAN -UAO)
>>> Unfortunately KVM with GICv3 is not currently supported.
>>> 
 I saw this error message regardless of how many vCPU I try to model.
 However, when I switch to machine-type of "VExpress-Gem5", the guest
 can boot, but it only allows up to 8 vCPUs. I suppose this is because
 in thi

[gem5-users] Re: Running script after boot in full-system mode

2021-03-23 Thread Wenqi Yin via gem5-users 
Hi Pedro, 

I am not sure about the status of the prebuilt images, but in my case I prepare 
the disk image myself and then install the m5 and a startup script as a systemd 
service, similar to the steps you referred at gem5 documentation page, step 4. 

However, the problem I had before is the startup script sometimes get killed 
during booting, the systemd log seems point the reason to the fact that the 
script is killed by a SIGHUP. My workaround is to disable the serial port in 
the config script (m5.disableAllListeners(), also I use my custom config 
script, not sure whether this line is already there in the default script like 
fs.py). Btw I just found this workaround and haven’t tested throughly yet, but 
so far seems it works. 

It’s just my workaround, and I am also curious about the status of the startup 
script, maybe others can complement. 

Best, 
Wenqi
> On Mar 23, 2021, at 08:37, Pedro Becker via gem5-users  
> wrote:
> 
> Hi all,
> 
> I'm trying to use the --script flag to run a script after boot in full-system 
> mode. However, the script is not executed; the terminal keeps waiting to be 
> used.
> Does anyone knows if the guest binaries 
> (https://www.gem5.org/documentation/general_docs/fullsystem/guest_binaries) 
> are prepared to run scripts passed through the --script flag (internally, 
> system.readfile)?
> Otherwise, is it necessary to create a disk from scratch and update the init 
> script as described here 
> https://www.gem5.org/documentation/general_docs/fullsystem/disks (Step 4) to 
> boot and run a script automatically? Are there pre-built images with those 
> steps performed?
> 
> Old questions/references directly use the --script option and do not mention 
> these additional steps:
> http://learning.gem5.org/book/part5/fs_config.html#using-a-runscript
> https://generic.wordpress.soton.ac.uk/arm/wp-content/uploads/sites/360/2016/10/gem5_tutorial.pdf
> https://spark.nitk.ac.in/r/GEM5-FS-Run.pdf
> https://gem5-users.gem5.narkive.com/ptGwsg8P/what-do-i-need-to-run-my-own-benchmark-on-full-system-mode
> 
> So I'm not sure how to proceed from here. 
> Any workaround to automatize a script execution after boot also works, if you 
> know any to share.
> 
> Thank you. 
> Pedro.
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[gem5-users] Re: CleanEvict packets in gem5

2021-03-03 Thread Wenqi Yin via gem5-users 
Hi Aritra, 

The CleanEvict packet don’t have data so it cannot do write in the cache. As 
Nikos said, the main purpose is to update the snoop filter. So when cache see a 
CleanEvict pkt, it either pass that pkt on to downstream when it misses the 
cache or stop the pkt if it hits. A side effect is when a cache see a 
CleanEvict and has the blk in its write queue, it indicates that blk don’t 
exist in peer caches so the wbpkt can clear the BlockCached bit if it’s 
original there. You can find this logic in cache/base.cc:1 
078~1093 under current release. 

Wenqi



> On Mar 3, 2021, at 13:37, bagchi95aritra--- via gem5-users 
>  wrote:
> 
> Hi Nikos, 
> 
> Thanks for your response. If possible, could you also indicate what gem5 
> cache does when it sees these CleanEvicts? If they are, as you said, write 
> backs originated for clean (not dirty) cache lines, then the cache shouldn’t 
> write the data. But then, what does it do? 
> 
> Thanks and regards,
> Aritra
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[gem5-users] Re: Using multiple threads on host?

2021-01-18 Thread Wenqi Yin via gem5-users 
No, in that case you need an arm64 host.

Wenqi

> On Jan 18, 2021, at 15:55, bodunhu--- via gem5-users  
> wrote:
> 
> I guess I forgot to mention that my host is X86_64 and the simulated 
> environment is aarch64 running Linux in full system mode. Does that still 
> apply to this scenario?
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[gem5-users] Re: Using multiple threads on host?

2021-01-18 Thread Wenqi Yin via gem5-users 
I think you can use KvmCPU to FF to the ROI and then started detailed 
simulation. KvmCPU is able to use multicores on your host, for detailed CPU 
simulation, I don’t think (but not completely sure, maybe others have better 
answers) you can use more than one host core. 

Wenqi
> On Jan 18, 2021, at 15:40, bodunhu--- via gem5-users  
> wrote:
> 
> Is there anyway to accelerate the simulation process possibly using multiple 
> threads on host? No matter how many CPUs I simulated it appears only one CPU 
> is actively used by gem5. Any help will be appreciated.
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[gem5-users] Re: How to use the new libm5.a

2020-10-28 Thread Wenqi Yin via gem5-users 
Hi Hoa, Gabe, 

Thanks for your help! But just want to confirm this: what I did in the past is 
calling map_m5_mem() in my code first and then call specific m5 functions, and 
it seems to work. The guest in running on KvmCPU. 

When I am trying to do the same thing with the new libm5.a, it gave an 
exception (Illegal Instruction), however I haven’t looked into the error 
carefully yet, it may just because for some reason the lib is still trying to 
use the magic instruction interface. But before I proceed any further, just 
want to make sure I was using the correct approach to do this. 

Best, 
Wenqi

> On Oct 26, 2020, at 23:30, Gabe Black via gem5-users  
> wrote:
> 
> Hi Wenqi. The updated libm5.a should be used in basically the same way as the 
> old version. Just link against the library, include the header file, and call 
> into the op you want using the normal function call syntax.
> 
> Hoa, the documentation you've linked to is a little out of date. How can it 
> be updated?
> 
> Gabe
> 
> On Sun, Oct 25, 2020 at 9:31 PM Hoa Nguyen via gem5-users 
> mailto:gem5-users@gem5.org>> wrote:
> Hi Wenqi,
> 
> We have some documentation about the new m5 utility here:
> https://www.gem5.org/documentation/general_docs/m5ops/ 
> 
> 
> The following link is an example of annotating PARSEC:
> https://github.com/darchr/parsec-benchmark/commits/gem5-20-annotations 
> 
> 
> Regards,
> Hoa Nguyen
> 
> On 10/25/20, wqyin--- via gem5-users  > wrote:
> > Hello all,
> >
> > I noticed the util/m5 has big changes since this
> > commit:26454e8072e607d54ac67c42b33355d7c94d6d60 around Apr 27. I am
> > wondering how should I use this new interface/implementation to call
> > m5ops in my program? Shall I also instantiate a default CallType and
> > then use it to obtain the dispatch table and finally pass it to
> > Command::run? Also is there any examples which use the new
> > implementation to annotate any benchmarks running inside gem5? Thanks
> >
> > Best,
> >
> > Wenqi
> >
> >
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[gem5-users] Re: How to use the new libm5.a

2020-10-28 Thread Wenqi Yin via gem5-users 
Hi Ciro, 

I don’t think things changed and your method should still work. However, my use 
case is a bit different as I need to call m5 ops when my guest is running on 
KVM cpu. My understanding is in virtual environment the magic Inst won’t work 
(I tested and it gave me Illegal Instruction exception) and I need to use the 
memory map interface, not sure if I understood correctly. But thanks for the 
suggestion, your way is definitely easier when it’s not in kvm. 

Best, 
Wenqi

> On Oct 27, 2020, at 07:34, Ciro Santilli via gem5-users  
> wrote:
> 
> Hi Wenqi,
> 
> Have you tried: 
> https://stackoverflow.com/questions/62757008/how-to-use-m5-in-gem5-20/62759204#62759204
>  
> 
>  or has something changed since then too? Seems to work on develop just now.
> From: wqyin--- via gem5-users 
> Sent: Sunday, October 25, 2020 7:36 PM
> To: gem5-users@gem5.org 
> Cc: wq...@utexas.edu 
> Subject: [gem5-users] How to use the new libm5.a
>  
> Hello all, 
> I noticed the util/m5 has big changes since this commit: 
> 26454e8072e607d54ac67c42b33355d7c94d6d60 around Apr 27. I am wondering how 
> should I use this new interface/implementation to call m5ops in my program? 
> Shall I also instantiate a default CallType and then use it to obtain the 
> dispatch table and finally pass it to Command::run? Also is there any 
> examples which use the new implementation to annotate any benchmarks running 
> inside gem5? Thanks
> Best,
> Wenqi
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[gem5-users] Simulation get significantly more slower with more guest cores using X86KvmCPU

2020-05-12 Thread Wenqi Yin via gem5-users 
Hello all, 

I am running FS simulation to boot a linux with the cpu type of X86KvmCPU. 
However, I observed the simulation get significantly slower once the number of 
cores of the guest exceed some value. 

I am using the config/example/fs.py  with the linux kernel and disking prepared 
according to this post: 
http://www.lowepower.com/jason/setting-up-gem5-full-system.html 
  to get the 
KVM work I applied two patches suggested by this post 
https://gem5-users.gem5.narkive.com/8DBihuUx/running-fs-py-with-x86kvmcpu-failed
 

  I specify the number of cores to the guest by cmd option -n of the fs.py 
script. I tested on two computers with 8 and 12 logical cores respectively, the 
simulation on the 8 core machine get slower once the guest has more than 4 
cores. On the 12 core machine, it get slower after 2 cores to the guest. QEMU 
running on the same computers don’t have this problem.

Any suggestions on what could be causing the problem? Thanks in advance. 

Best, 
Wenqi___
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