Re: [gem5-users] Getting single cache line from multiple channels of HBM
Hi Chenfeng, Sorry for the late response. If you look into src/mem/Xbar.py the width of SystemXbar is set to be 16-bytes. This means if you are running the network at 1GHz, even though your HBM can support 128 GBps (with 8 channels), the bandwidth from crossbar is 16*1 GHz = 16GBps. There might be multiple ways to solve this issue. One way is to just increase the SystemXbar width from 16-bytes to 128 bytes. Then you should be able to achieve 128 GBps. Let me know if this helps. Thanks, Nitish On Tue, Sep 17, 2019 at 5:15 PM Zhao, Chenfeng wrote: > Hi Nitish, > > I am also trying to use 8 channels of HBM to take advantage of 128Gbps > bandwidth. However, I can only get 16GBps as well. I was wondering have you > figured out how to solve this problem? > > Thanks a lot! > > Chenfeng Zhao > > ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] Getting single cache line from multiple channels of HBM
Hi Nitish, I am also trying to use 8 channels of HBM to take advantage of 128Gbps bandwidth. However, I can only get 16GBps as well. I was wondering have you figured out how to solve this problem? Thanks a lot! Chenfeng Zhao ___ gem5-users mailing list gem5-users@gem5.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
[gem5-users] Getting single cache line from multiple channels of HBM
Hi,
I have a streaming application which reads two arrays A and B sequentially
from the memory. I am trying to use HBM memory model (HBM_1000_4H_1x128) in
gem5 with 8 channels (without ruby). Since there are 8 channels and each
can provide 16 GBps, I want to achieve 8x16 = 128 GBps while reading a
single cache line from memory. I guess this is only possible when the lower
address bits are mapped to different channels? Out of the three address
mappings “RoRaBaChCo”, “RoRaBaCoCh” and “RoCoRaBaCh” supported in gem5 only
“RoRaBaCoCh” and “RoCoRaBaCh” allow the channel bits to be at LSB
positions. However, in dram_ctrl.cc in DRAMCtrl::init() there is an
assertion which ensures that an entire cache line is mapped to a single
channel which is preventing me to map a single cache line to multiple
channels.
if (system()->cacheLineSize() > range.granularity()) {
fatal("Channel interleaving of %s must be at least as large "
"as the cache line size\n", name());
}
Is there a way I can achieve 128 GBps for this streaming application? Let
me know if you have suggestions. I tried running for different settings and
memory configurations but the achieved bandwidth is much lower than
128GBps. I also integrated the changes as mentioned in
https://www.mail-archive.com/gem5-users@gem5.org/msg16420.html but it
didn’t help either.
Thanks,
Nitish
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