Hello everyone I’m an undergraduate student and going to embark on a journey to extend the protocol for MESI_Three_Level at the memory level to MSI or MESI, as opposed to the two-state MI that it is right now. Does anyone have any tips or advice for this journey, perhaps one of you has done something similar or already have this implemented?
I understand that at a minimum, this requires modifying both the memory SLICC protocol and also the last level cache. Thanks a lot, Arteen UCLA _______________________________________________ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org
