gem5 does not write UART output to the console, it writes it to a file in
the m5out directory, and makes it available if you connect to the console
output socket using m5term (or any other telnet client). If you use
aggressive debug flags like ExecAll, that will slow down execution
dramatically and may prevent you from getting to the code you're interested
in in a reasonable amount of time.

Gabe

On Sun, Oct 31, 2021 at 4:51 PM Arrvindh Shriraman via gem5-users <
gem5-users@gem5.org> wrote:

> Hi —
>
> I am trying to set up a bare-metal execution for RISC-V.
> I am using the following template
>
> https://github.com/s094392/riscv-bare-metal
>
> However the bytes I send to the uart do not appear on gem5 terminal
> output. Not sure if they are getting to the uart either
>     - uart (
> https://github.com/s094392/riscv-bare-metal/blob/master/inc/uart.h)
>
> I am trying this on the gem5 21.
> $ ./build/RISCV/gem5.opt --debug-start=0 --debug-file=trace.out
> --debug-flags=Event,ExecAll,FmtFlag ./configs/example/riscv/fs_linux.py
> --bare-metal --kernel ../riscv-bare-metal/kernel.elf
>
>
> On qemu the exact same program results in the following output.
> qemu-system-riscv64 -M virt -kernel kernel.img -bios none -serial stdio
> -display none
> Timer Interrupt: 1
> Timer Interrupt: 2
> Timer Interrupt: 3
> Timer Interrupt: 4
> Timer Interrupt: 5
> Timer Interrupt: 6
>
>
>
> Not sure why the example works on qemu but not gem5 atomic. Any
> suggestions welcome.
>
> Regards,
> Arrvindh Shriraman
> Associate Professor
> Computer Science
> Simon Fraser University
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