Are you sure its actually ignoring dependencies? Run with
--debug-flags=IntRegs,FloatRegs. To verify what vdivs wrote and what vstr
read.
I'd assume it's just a bug in the gem5 generateDissasembly routine printing
out the instruction format. It probably just passed reg 15, meaning
floating point reg 15 and the routine assumed it was integer reg 15 (which
is the pc on arm).
On Wed, Jul 16, 2014 at 3:41 PM, Namitha Krishna via gem5-users
gem5-users@gem5.org wrote:
Hello all,
I'm working with the arm-detailed core in gem5. I'm trying to compare
execution times of some floating point programs on cortex A9 hardware using
cycle count register and my configured gem5 model (configured for cortex
A9). I'm observing some strange behaviour with decoding of load and store
instructions in gem5. The following instructions:
vdivs s15, s14, s15
vstr s15,[r3,#0]
is getting decoded as
vdivs f15,f14,f15
vstr pc,[r3,#0]
in gem5.
I see these are the instructions fetched when I turn on
--debug-flag=Fetch. Alos, I'm observing this behaviour only for load store
instructions with s15 as the register operands.
any idea why this could be happening? I'm compiling the binaries with no
optimization level and -mfpu=vfpv3 and -mfloat=softfp. I'm using the
arm-xilinx-none-eabi tool chain for both the binaries: one running on the
hardware and one running in gem5. Because of the above bug, true
dependencies are getting killed and gem5 is faster than hardware leading to
around 7-12% error. I'm confident of my configuration as I'm getting less
than 1% error for integer programs.
Please tell me what I could do to solve this issue or if I'm overlooking
something as soon as possible as the dealine for my thesis is approaching
soon. I have the latest gem5-dev repository cloned.
Thanks!
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