Kévin Redon has uploaded this change for review. (
https://gerrit.osmocom.org/13054
Change subject: add RMII clock output
..
add RMII clock output
The TLK106 Ethernet PHY requires a 50 MHz input on XI in RMII mode.
RMII_CLOCK is connected on the micro-controller on PA14 and PB11.
PA14, with note "GTXCR" on the schematic, cannot be use to provide
the 50 MHz clock since this is the clock output for GLK[0], which
is reserved for the CPU running at 120 MHz.
PB11 is the clock output pin for GCLK[5], which now divides DPLL1
at 100 MHz to the required 50 MHz.
WARNING: I did not test if the output clock signal matches the
requirement of the input clock signal.
Change-Id: Id8409779d2835b56bbae7db2e962034c82fa3b62
---
M sysmoOCTSIM/atmel_start_config.atstart
M sysmoOCTSIM/atmel_start_pins.h
M sysmoOCTSIM/config/hpl_gclk_config.h
M sysmoOCTSIM/driver_init.c
4 files changed, 52 insertions(+), 2 deletions(-)
git pull ssh://gerrit.osmocom.org:29418/osmo-ccid-firmware
refs/changes/54/13054/1
diff --git a/sysmoOCTSIM/atmel_start_config.atstart
b/sysmoOCTSIM/atmel_start_config.atstart
index 4590623..29ec468 100644
--- a/sysmoOCTSIM/atmel_start_config.atstart
+++ b/sysmoOCTSIM/atmel_start_config.atstart
@@ -734,7 +734,7 @@
gclk_gen_4_div: 1
gclk_gen_4_div_sel: false
gclk_gen_4_oscillator: External Crystal Oscillator 8-48MHz (XOSC1)
- gclk_gen_5_div: 5
+ gclk_gen_5_div: 2
gclk_gen_5_div_sel: false
gclk_gen_5_oscillator: Digital Phase Locked Loop (DPLL1)
gclk_gen_6_div: 1
@@ -1453,6 +1453,16 @@
pad_function: M
pad_initial_level: Low
pad_pull_config: 'Off'
+ RMII_CLOCK:
+name: PB11
+definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::pad::PB11
+mode: Advanced
+user_label: RMII_CLOCK
+configuration:
+ pad_direction: Out
+ pad_function: M
+ pad_initial_level: Low
+ pad_pull_config: 'Off'
SCL1:
name: PB14
definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::pad::PB14
diff --git a/sysmoOCTSIM/atmel_start_pins.h b/sysmoOCTSIM/atmel_start_pins.h
index c877d5e..18a55fa 100644
--- a/sysmoOCTSIM/atmel_start_pins.h
+++ b/sysmoOCTSIM/atmel_start_pins.h
@@ -46,6 +46,7 @@
#define SCL3 GPIO(GPIO_PORTB, 6)
#define SDA3 GPIO(GPIO_PORTB, 7)
#define SIM4_IO GPIO(GPIO_PORTB, 8)
+#define RMII_CLOCK GPIO(GPIO_PORTB, 11)
#define SCL1 GPIO(GPIO_PORTB, 14)
#define SDA1 GPIO(GPIO_PORTB, 15)
#define SIM5_IO GPIO(GPIO_PORTB, 16)
diff --git a/sysmoOCTSIM/config/hpl_gclk_config.h
b/sysmoOCTSIM/config/hpl_gclk_config.h
index 6b7586c..8c0beee 100644
--- a/sysmoOCTSIM/config/hpl_gclk_config.h
+++ b/sysmoOCTSIM/config/hpl_gclk_config.h
@@ -454,7 +454,7 @@
// Generic clock generator 5 division <0x-0x>
// gclk_gen_5_div
#ifndef CONF_GCLK_GEN_5_DIV
-#define CONF_GCLK_GEN_5_DIV 5
+#define CONF_GCLK_GEN_5_DIV 2
#endif
//
//
diff --git a/sysmoOCTSIM/driver_init.c b/sysmoOCTSIM/driver_init.c
index e56ba0d..ef9c56b 100644
--- a/sysmoOCTSIM/driver_init.c
+++ b/sysmoOCTSIM/driver_init.c
@@ -691,6 +691,45 @@
gpio_set_pin_function(SDA3, GPIO_PIN_FUNCTION_OFF);
+ // GPIO on PB11
+
+ gpio_set_pin_direction(RMII_CLOCK,
+ // Pin direction
+ // pad_direction
+ // Off
+ // In
+ // Out
+ GPIO_DIRECTION_OUT);
+
+ gpio_set_pin_level(RMII_CLOCK,
+ // Initial level
+ // pad_initial_level
+ // Low
+ // High
+ false);
+
+ gpio_set_pin_function(RMII_CLOCK,
+ // Pin function
+ // pad_function
+ // Auto : use driver pinmux if signal is
imported by driver, else turn off function
+ // Auto
+ // Off
+ // A
+ // B
+ // C
+ // D
+ // E
+ // F
+ // G
+ // H
+ // I
+ // J
+ // K
+ // L
+ // M
+ // N
+ GPIO_PIN_FUNCTION_M);
+
// GPIO on PB14
gpio_set_pin_level(SCL1,
--
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Gerrit-Project: osmo-ccid-firmware
Gerrit-Branch: master
Gerrit-MessageType: newchange
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