Change in osmo-ccid-firmware[master]: output 50 MHz for RMII
Harald Welte has submitted this change and it was merged. ( https://gerrit.osmocom.org/13780 ) Change subject: output 50 MHz for RMII .. output 50 MHz for RMII in hardware revision 2 the Ethernet PHY RMII_CLOCK input clock is connected to the MCU pin PA10. GCLK4 of the MCU now outputs the required 50 MHz clock on this pin. the same clock is re-used for UART debug to generate the 921600 bps baud rate. Change-Id: Id3a3dee15c3986536b0623d0f39ca62e94acd1fd --- M sysmoOCTSIM/atmel_start_config.atstart M sysmoOCTSIM/atmel_start_pins.h M sysmoOCTSIM/config/hpl_gclk_config.h M sysmoOCTSIM/config/peripheral_clk_config.h M sysmoOCTSIM/driver_init.c 5 files changed, 63 insertions(+), 5 deletions(-) Approvals: Jenkins Builder: Verified Harald Welte: Looks good to me, approved diff --git a/sysmoOCTSIM/atmel_start_config.atstart b/sysmoOCTSIM/atmel_start_config.atstart index 4fda2f8..6357a74 100644 --- a/sysmoOCTSIM/atmel_start_config.atstart +++ b/sysmoOCTSIM/atmel_start_config.atstart @@ -702,7 +702,7 @@ gclk_arch_gen_3_runstdby: false gclk_arch_gen_4_enable: true gclk_arch_gen_4_idc: false - gclk_arch_gen_4_oe: false + gclk_arch_gen_4_oe: true gclk_arch_gen_4_oov: false gclk_arch_gen_4_runstdby: false gclk_arch_gen_5_enable: true @@ -748,7 +748,7 @@ gclk_gen_3_div: 1 gclk_gen_3_div_sel: false gclk_gen_3_oscillator: 32kHz External Crystal Oscillator (XOSC32K) - gclk_gen_4_div: 1 + gclk_gen_4_div: 2 gclk_gen_4_div_sel: false gclk_gen_4_oscillator: Digital Phase Locked Loop (DPLL1) gclk_gen_5_div: 5 @@ -1462,6 +1462,16 @@ mode: Peripheral IO user_label: SIM2_IO configuration: null + RMII_CLOCK: +name: PA10 +definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::pad::PA10 +mode: Advanced +user_label: RMII_CLOCK +configuration: + pad_direction: Out + pad_function: M + pad_initial_level: Low + pad_pull_config: 'Off' SIMCLK_20MHZ: name: PA11 definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::pad::PA11 diff --git a/sysmoOCTSIM/atmel_start_pins.h b/sysmoOCTSIM/atmel_start_pins.h index 0264736..7cbaed5 100644 --- a/sysmoOCTSIM/atmel_start_pins.h +++ b/sysmoOCTSIM/atmel_start_pins.h @@ -31,6 +31,7 @@ #define SIM5_INT GPIO(GPIO_PORTA, 3) #define SIM0_IO GPIO(GPIO_PORTA, 4) #define SIM2_IO GPIO(GPIO_PORTA, 9) +#define RMII_CLOCK GPIO(GPIO_PORTA, 10) #define SIMCLK_20MHZ GPIO(GPIO_PORTA, 11) #define SIM1_IO GPIO(GPIO_PORTA, 16) #define VB0 GPIO(GPIO_PORTA, 20) diff --git a/sysmoOCTSIM/config/hpl_gclk_config.h b/sysmoOCTSIM/config/hpl_gclk_config.h index 71c26e1..81a1f03 100644 --- a/sysmoOCTSIM/config/hpl_gclk_config.h +++ b/sysmoOCTSIM/config/hpl_gclk_config.h @@ -349,7 +349,7 @@ // Indicates whether Output Enable is enabled or not // gclk_arch_gen_4_oe #ifndef CONF_GCLK_GEN_4_OE -#define CONF_GCLK_GEN_4_OE 0 +#define CONF_GCLK_GEN_4_OE 1 #endif // Output Off Value @@ -378,7 +378,7 @@ // Generic clock generator 4 division <0x-0x> // gclk_gen_4_div #ifndef CONF_GCLK_GEN_4_DIV -#define CONF_GCLK_GEN_4_DIV 1 +#define CONF_GCLK_GEN_4_DIV 2 #endif // // diff --git a/sysmoOCTSIM/config/peripheral_clk_config.h b/sysmoOCTSIM/config/peripheral_clk_config.h index 4bff6ff..2ae1f63 100644 --- a/sysmoOCTSIM/config/peripheral_clk_config.h +++ b/sysmoOCTSIM/config/peripheral_clk_config.h @@ -641,7 +641,7 @@ * \brief SERCOM7's Core Clock frequency */ #ifndef CONF_GCLK_SERCOM7_CORE_FREQUENCY -#define CONF_GCLK_SERCOM7_CORE_FREQUENCY 1 +#define CONF_GCLK_SERCOM7_CORE_FREQUENCY 5000 #endif /** diff --git a/sysmoOCTSIM/driver_init.c b/sysmoOCTSIM/driver_init.c index 0b6b190..1233d02 100644 --- a/sysmoOCTSIM/driver_init.c +++ b/sysmoOCTSIM/driver_init.c @@ -503,6 +503,53 @@ gpio_set_pin_function(SIM5_INT, GPIO_PIN_FUNCTION_OFF); + // GPIO on PA10 + + gpio_set_pin_direction(RMII_CLOCK, + // Pin direction + // pad_direction + // Off + // In + // Out + GPIO_DIRECTION_OUT); + + gpio_set_pin_level(RMII_CLOCK, + // Initial level + // pad_initial_level + // Low + // High + false); + + gpio_set_pin_pull_mode(RMII_CLOCK, + // Pull configuration + // pad_pull_config + // Off + // Pull-up + // Pull-down + GPIO_PULL_OFF); + + gpio_set_pin_function(RMII_CLOCK, + // Pin function + //
Change in osmo-ccid-firmware[master]: output 50 MHz for RMII
Harald Welte has posted comments on this change. ( https://gerrit.osmocom.org/13780 ) Change subject: output 50 MHz for RMII .. Patch Set 1: Code-Review+2 -- To view, visit https://gerrit.osmocom.org/13780 To unsubscribe, or for help writing mail filters, visit https://gerrit.osmocom.org/settings Gerrit-Project: osmo-ccid-firmware Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id3a3dee15c3986536b0623d0f39ca62e94acd1fd Gerrit-Change-Number: 13780 Gerrit-PatchSet: 1 Gerrit-Owner: Kévin Redon Gerrit-Reviewer: Harald Welte Gerrit-Reviewer: Jenkins Builder (102) Gerrit-Comment-Date: Thu, 25 Apr 2019 19:50:20 + Gerrit-HasComments: No Gerrit-HasLabels: Yes
Change in osmo-ccid-firmware[master]: output 50 MHz for RMII
Kévin Redon has uploaded this change for review. ( https://gerrit.osmocom.org/13780 Change subject: output 50 MHz for RMII .. output 50 MHz for RMII in hardware revision 2 the Ethernet PHY RMII_CLOCK input clock is connected to the MCU pin PA10. GCLK4 of the MCU now outputs the required 50 MHz clock on this pin. the same clock is re-used for UART debug to generate the 921600 bps baud rate. Change-Id: Id3a3dee15c3986536b0623d0f39ca62e94acd1fd --- M sysmoOCTSIM/atmel_start_config.atstart M sysmoOCTSIM/atmel_start_pins.h M sysmoOCTSIM/config/hpl_gclk_config.h M sysmoOCTSIM/config/peripheral_clk_config.h M sysmoOCTSIM/driver_init.c 5 files changed, 63 insertions(+), 5 deletions(-) git pull ssh://gerrit.osmocom.org:29418/osmo-ccid-firmware refs/changes/80/13780/1 diff --git a/sysmoOCTSIM/atmel_start_config.atstart b/sysmoOCTSIM/atmel_start_config.atstart index 4fda2f8..6357a74 100644 --- a/sysmoOCTSIM/atmel_start_config.atstart +++ b/sysmoOCTSIM/atmel_start_config.atstart @@ -702,7 +702,7 @@ gclk_arch_gen_3_runstdby: false gclk_arch_gen_4_enable: true gclk_arch_gen_4_idc: false - gclk_arch_gen_4_oe: false + gclk_arch_gen_4_oe: true gclk_arch_gen_4_oov: false gclk_arch_gen_4_runstdby: false gclk_arch_gen_5_enable: true @@ -748,7 +748,7 @@ gclk_gen_3_div: 1 gclk_gen_3_div_sel: false gclk_gen_3_oscillator: 32kHz External Crystal Oscillator (XOSC32K) - gclk_gen_4_div: 1 + gclk_gen_4_div: 2 gclk_gen_4_div_sel: false gclk_gen_4_oscillator: Digital Phase Locked Loop (DPLL1) gclk_gen_5_div: 5 @@ -1462,6 +1462,16 @@ mode: Peripheral IO user_label: SIM2_IO configuration: null + RMII_CLOCK: +name: PA10 +definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::pad::PA10 +mode: Advanced +user_label: RMII_CLOCK +configuration: + pad_direction: Out + pad_function: M + pad_initial_level: Low + pad_pull_config: 'Off' SIMCLK_20MHZ: name: PA11 definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::pad::PA11 diff --git a/sysmoOCTSIM/atmel_start_pins.h b/sysmoOCTSIM/atmel_start_pins.h index 0264736..7cbaed5 100644 --- a/sysmoOCTSIM/atmel_start_pins.h +++ b/sysmoOCTSIM/atmel_start_pins.h @@ -31,6 +31,7 @@ #define SIM5_INT GPIO(GPIO_PORTA, 3) #define SIM0_IO GPIO(GPIO_PORTA, 4) #define SIM2_IO GPIO(GPIO_PORTA, 9) +#define RMII_CLOCK GPIO(GPIO_PORTA, 10) #define SIMCLK_20MHZ GPIO(GPIO_PORTA, 11) #define SIM1_IO GPIO(GPIO_PORTA, 16) #define VB0 GPIO(GPIO_PORTA, 20) diff --git a/sysmoOCTSIM/config/hpl_gclk_config.h b/sysmoOCTSIM/config/hpl_gclk_config.h index 71c26e1..81a1f03 100644 --- a/sysmoOCTSIM/config/hpl_gclk_config.h +++ b/sysmoOCTSIM/config/hpl_gclk_config.h @@ -349,7 +349,7 @@ // Indicates whether Output Enable is enabled or not // gclk_arch_gen_4_oe #ifndef CONF_GCLK_GEN_4_OE -#define CONF_GCLK_GEN_4_OE 0 +#define CONF_GCLK_GEN_4_OE 1 #endif // Output Off Value @@ -378,7 +378,7 @@ // Generic clock generator 4 division <0x-0x> // gclk_gen_4_div #ifndef CONF_GCLK_GEN_4_DIV -#define CONF_GCLK_GEN_4_DIV 1 +#define CONF_GCLK_GEN_4_DIV 2 #endif // // diff --git a/sysmoOCTSIM/config/peripheral_clk_config.h b/sysmoOCTSIM/config/peripheral_clk_config.h index 4bff6ff..2ae1f63 100644 --- a/sysmoOCTSIM/config/peripheral_clk_config.h +++ b/sysmoOCTSIM/config/peripheral_clk_config.h @@ -641,7 +641,7 @@ * \brief SERCOM7's Core Clock frequency */ #ifndef CONF_GCLK_SERCOM7_CORE_FREQUENCY -#define CONF_GCLK_SERCOM7_CORE_FREQUENCY 1 +#define CONF_GCLK_SERCOM7_CORE_FREQUENCY 5000 #endif /** diff --git a/sysmoOCTSIM/driver_init.c b/sysmoOCTSIM/driver_init.c index 0b6b190..1233d02 100644 --- a/sysmoOCTSIM/driver_init.c +++ b/sysmoOCTSIM/driver_init.c @@ -503,6 +503,53 @@ gpio_set_pin_function(SIM5_INT, GPIO_PIN_FUNCTION_OFF); + // GPIO on PA10 + + gpio_set_pin_direction(RMII_CLOCK, + // Pin direction + // pad_direction + // Off + // In + // Out + GPIO_DIRECTION_OUT); + + gpio_set_pin_level(RMII_CLOCK, + // Initial level + // pad_initial_level + // Low + // High + false); + + gpio_set_pin_pull_mode(RMII_CLOCK, + // Pull configuration + // pad_pull_config + // Off + // Pull-up + // Pull-down + GPIO_PULL_OFF); + + gpio_set_pin_function(RMII_CLOCK, + // Pin function + //
