Re: CS/CDS instruction

2023-03-17 Thread Ed Jaffe

On 3/17/2023 10:27 AM, Peter Relson wrote:

And it's fair to wonder. We do "cheat" and turn off facility bits in "our copy" that 
relate to facilities that the customer, via MACHMIG, has asked not to be exploited for migration reasons. In 
practice, for those facilities it is not relevant whether the facility bit is on, because there is an 
operating-system-provided bit that is supposed to be checked to tell if it is OK with the OS for you to use 
it. IHAFACL, for example, has this comment for facility bit 129: "Even if this bit is on, do not use the 
VEF unless bit CVTVEF is on".


It's good you publish have admonishments like that.

Programmers do not like to load extra base registers if they do not need to.

PSA is conveniently addressable to everyone all the time in any 
environment. Getting to the CVT takes overt action *and* an available 
register...



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Re: CS/CDS instruction

2023-03-17 Thread Peter Relson
Ed J wrote

What about MACHMIG? Do you turn off the bit(s) corresponding to a
facility that we wish to pretend does not exist via LOADxx specification?


And it's fair to wonder. We do "cheat" and turn off facility bits in "our copy" 
that relate to facilities that the customer, via MACHMIG, has asked not to be 
exploited for migration reasons. In practice, for those facilities it is not 
relevant whether the facility bit is on, because there is an 
operating-system-provided bit that is supposed to be checked to tell if it is 
OK with the OS for you to use it. IHAFACL, for example, has this comment for 
facility bit 129: "Even if this bit is on, do not use the VEF unless bit CVTVEF 
is on".

Peter Relson
z/OS Core Technology Design


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Re: CS/CDS instruction

2023-03-16 Thread Ed Jaffe

On 3/16/2023 5:15 AM, Peter Relson wrote:

The only difference between "your" STFLE and "our" STFLE is that the z/OS one 
is done only once, at IPL.
If some facility arrived after IPL, you could find it with "your" STFLE That is 
far from a frequent occurrence.


What about MACHMIG? Do you turn off the bit(s) corresponding to a 
facility that we wish to pretend does not exist via LOADxx specification?



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Re: CS/CDS instruction

2023-03-16 Thread Peter Relson

Or you just could do an STFLE and check the facility bits...


Or your could use the facility bit area that z/OS set up for you. That's easier.

That is mapped by IHAFACL and the area is pointed to by ECVTFACL (this has 
existed since z/OS 2.1).
A subset of those bits are also mapped within the facilities list area of 
FLCFACL/FLCFACLE in IHAPSA or FlceFacilitiesList / FlceFacilitiesList1 in 
IHAPSAE (the IHAFACL DSECT can be used there too, at least for the first 256 
facility bits which covers all that currently exist but eventually there could 
be more).

IHAFACL does not map every bit, because some have seemed unnecessary to know 
about. If there's something missing that you feel appropriate to code to, feel 
free to let us know.

The only difference between "your" STFLE and "our" STFLE is that the z/OS one 
is done only once, at IPL.
If some facility arrived after IPL, you could find it with "your" STFLE That is 
far from a frequent occurrence.

Peter Relson
z/OS Core Technology Design

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Re: CS/CDS instruction

2023-03-15 Thread John Dravnieks
On z/OS 2.2 or later, the result from STFLE is stored in the PSA at offset 200 
(X'C8')  - look at IHAPSAE  field name FLCEFACILITIESLIST  (and this is a PI 
field)

Kind regards
John

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Re: CS/CDS instruction

2023-03-15 Thread Joe Monk
Or you just could do an STFLE and check the facility bits...

Joe

On Wed, Mar 15, 2023 at 10:52 AM P H <
04843e86df79-dmarc-requ...@listserv.ua.edu> wrote:

> This doc (url below) will give you a list of what is available/supported
> on different generations of the current System z. However if you want to
> know about a specific system you have then discuss with your IBM Rep who
> will be able to give you a complete list of features (VPD) for your System.
>
> https://www.redbooks.ibm.com/abstracts/redp5157.html
>
> Regards
>
> Parwez Hamid​
> 
> From: IBM Mainframe Discussion List  on behalf
> of Ituriel do Neto <03427ec2837d-dmarc-requ...@listserv.ua.edu>
> Sent: 15 March 2023 13:30
> To: IBM-MAIN@LISTSERV.UA.EDU 
> Subject: Re: CS/CDS instruction
>
> Can we detect if a specific feature is available in the current hardware?
>
>
> Best Regards
>
> Ituriel do Nascimento Neto
> z/OS System Programmer
>
>
>
>
>
>
> Em sábado, 11 de março de 2023 às 14:05:12 BRT, Paul Gilmartin <
> 042bfe9c879d-dmarc-requ...@listserv.ua.edu> escreveu:
>
>
>
>
>
> On Sat, 11 Mar 2023 00:03:06 -0800, Leonard D Woren wrote:
>
> >If some particular instruction set feature is installed, the
> >definition of ASI/AGSI is enhanced to serialize the update, making it
> >a simpler solution than a CDS loop or PLO.
> >
> >In some performance testing a while back on a z14 or z15 which I think
> >had the above serialization feature, the execution times for a very
> >large number of executions of L / AHI / ST were very close to the same
> >count of ASI.  If I recall, the ASI was a few percent slower, I guess
> >because of the serialization.  I.e., unless you're doing abnormal
> >tests as I did, you won't notice the difference.
> >
>
> From the PoOps (excerpted):
>   The storage-operand update reference for the follow- ing
>   instructions appears to be an interlocked-update reference as
>   observed by other CPUs and channel programs.
>
> • TEST AND SET
> • COMPARE AND SWAP
> (of course)
>
> • AND (NI and NIY), when the interlocked-access facility 2 is installed
> • OR (OI and OIY), when the interlocked-access facility 2 is installed
> (at last!)
>
> • ADD IMMEDIATE (ASI and AGSI), when the interlocked-access facility
>   1 is installed and the first operand is aligned on an integral
>   boundary corresponding to its size
>
> The feature-dependent instructions are treacherous.  Programmers must
> avoid them in multi-tasking code intended to be portable.
>
> I consider it bad hardware design to introduce feature-dependent
> instructions.  They should have remained invalid operations on models
> lacking the interlock facility.
>
> I believe NI and OI are primeval: they antedate multiprocessors and
> became unsafe only at the advent of multiprocessors.
>
> --
> gil
>
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Re: CS/CDS instruction

2023-03-15 Thread P H
This doc (url below) will give you a list of what is available/supported on 
different generations of the current System z. However if you want to know 
about a specific system you have then discuss with your IBM Rep who will be 
able to give you a complete list of features (VPD) for your System.

https://www.redbooks.ibm.com/abstracts/redp5157.html

Regards

Parwez Hamid​

From: IBM Mainframe Discussion List  on behalf of 
Ituriel do Neto <03427ec2837d-dmarc-requ...@listserv.ua.edu>
Sent: 15 March 2023 13:30
To: IBM-MAIN@LISTSERV.UA.EDU 
Subject: Re: CS/CDS instruction

Can we detect if a specific feature is available in the current hardware?


Best Regards

Ituriel do Nascimento Neto
z/OS System Programmer






Em sábado, 11 de março de 2023 às 14:05:12 BRT, Paul Gilmartin 
<042bfe9c879d-dmarc-requ...@listserv.ua.edu> escreveu:





On Sat, 11 Mar 2023 00:03:06 -0800, Leonard D Woren wrote:

>If some particular instruction set feature is installed, the
>definition of ASI/AGSI is enhanced to serialize the update, making it
>a simpler solution than a CDS loop or PLO.
>
>In some performance testing a while back on a z14 or z15 which I think
>had the above serialization feature, the execution times for a very
>large number of executions of L / AHI / ST were very close to the same
>count of ASI.  If I recall, the ASI was a few percent slower, I guess
>because of the serialization.  I.e., unless you're doing abnormal
>tests as I did, you won't notice the difference.
>

From the PoOps (excerpted):
  The storage-operand update reference for the follow- ing
  instructions appears to be an interlocked-update reference as
  observed by other CPUs and channel programs.

• TEST AND SET
• COMPARE AND SWAP
(of course)

• AND (NI and NIY), when the interlocked-access facility 2 is installed
• OR (OI and OIY), when the interlocked-access facility 2 is installed
(at last!)

• ADD IMMEDIATE (ASI and AGSI), when the interlocked-access facility
  1 is installed and the first operand is aligned on an integral
  boundary corresponding to its size

The feature-dependent instructions are treacherous.  Programmers must
avoid them in multi-tasking code intended to be portable.

I consider it bad hardware design to introduce feature-dependent
instructions.  They should have remained invalid operations on models
lacking the interlock facility.

I believe NI and OI are primeval: they antedate multiprocessors and
became unsafe only at the advent of multiprocessors.

--
gil

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Re: CS/CDS instruction

2023-03-15 Thread Seymour J Metz
Yes, with STFL.


--
Shmuel (Seymour J.) Metz
http://mason.gmu.edu/~smetz3


From: IBM Mainframe Discussion List [IBM-MAIN@LISTSERV.UA.EDU] on behalf of 
Ituriel do Neto [03427ec2837d-dmarc-requ...@listserv.ua.edu]
Sent: Wednesday, March 15, 2023 9:30 AM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: Re: CS/CDS instruction

Can we detect if a specific feature is available in the current hardware?


Best Regards

Ituriel do Nascimento Neto
z/OS System Programmer






Em sábado, 11 de março de 2023 às 14:05:12 BRT, Paul Gilmartin 
<042bfe9c879d-dmarc-requ...@listserv.ua.edu> escreveu:





On Sat, 11 Mar 2023 00:03:06 -0800, Leonard D Woren wrote:

>If some particular instruction set feature is installed, the
>definition of ASI/AGSI is enhanced to serialize the update, making it
>a simpler solution than a CDS loop or PLO.
>
>In some performance testing a while back on a z14 or z15 which I think
>had the above serialization feature, the execution times for a very
>large number of executions of L / AHI / ST were very close to the same
>count of ASI.  If I recall, the ASI was a few percent slower, I guess
>because of the serialization.  I.e., unless you're doing abnormal
>tests as I did, you won't notice the difference.
>

>From the PoOps (excerpted):
  The storage-operand update reference for the follow- ing
  instructions appears to be an interlocked-update reference as
  observed by other CPUs and channel programs.

• TEST AND SET
• COMPARE AND SWAP
(of course)

• AND (NI and NIY), when the interlocked-access facility 2 is installed
• OR (OI and OIY), when the interlocked-access facility 2 is installed
(at last!)

• ADD IMMEDIATE (ASI and AGSI), when the interlocked-access facility
  1 is installed and the first operand is aligned on an integral
  boundary corresponding to its size

The feature-dependent instructions are treacherous.  Programmers must
avoid them in multi-tasking code intended to be portable.

I consider it bad hardware design to introduce feature-dependent
instructions.  They should have remained invalid operations on models
lacking the interlock facility.

I believe NI and OI are primeval: they antedate multiprocessors and
became unsafe only at the advent of multiprocessors.

--
gil

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Re: CS/CDS instruction

2023-03-15 Thread Ituriel do Neto
Can we detect if a specific feature is available in the current hardware?


Best Regards

Ituriel do Nascimento Neto
z/OS System Programmer






Em sábado, 11 de março de 2023 às 14:05:12 BRT, Paul Gilmartin 
<042bfe9c879d-dmarc-requ...@listserv.ua.edu> escreveu: 





On Sat, 11 Mar 2023 00:03:06 -0800, Leonard D Woren wrote:

>If some particular instruction set feature is installed, the 
>definition of ASI/AGSI is enhanced to serialize the update, making it 
>a simpler solution than a CDS loop or PLO.
>
>In some performance testing a while back on a z14 or z15 which I think 
>had the above serialization feature, the execution times for a very 
>large number of executions of L / AHI / ST were very close to the same 
>count of ASI.  If I recall, the ASI was a few percent slower, I guess 
>because of the serialization.  I.e., unless you're doing abnormal 
>tests as I did, you won't notice the difference.
>

>From the PoOps (excerpted):
  The storage-operand update reference for the follow- ing
  instructions appears to be an interlocked-update reference as
  observed by other CPUs and channel programs.

• TEST AND SET
• COMPARE AND SWAP
(of course)

• AND (NI and NIY), when the interlocked-access facility 2 is installed
• OR (OI and OIY), when the interlocked-access facility 2 is installed
(at last!)

• ADD IMMEDIATE (ASI and AGSI), when the interlocked-access facility
  1 is installed and the first operand is aligned on an integral
  boundary corresponding to its size

The feature-dependent instructions are treacherous.  Programmers must
avoid them in multi-tasking code intended to be portable.

I consider it bad hardware design to introduce feature-dependent
instructions.  They should have remained invalid operations on models
lacking the interlock facility.

I believe NI and OI are primeval: they antedate multiprocessors and
became unsafe only at the advent of multiprocessors.

-- 
gil

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Re: CS/CDS instruction

2023-03-11 Thread Paul Gilmartin
On Sat, 11 Mar 2023 00:03:06 -0800, Leonard D Woren wrote:

>If some particular instruction set feature is installed, the 
>definition of ASI/AGSI is enhanced to serialize the update, making it 
>a simpler solution than a CDS loop or PLO.
>
>In some performance testing a while back on a z14 or z15 which I think 
>had the above serialization feature, the execution times for a very 
>large number of executions of L / AHI / ST were very close to the same 
>count of ASI.  If I recall, the ASI was a few percent slower, I guess 
>because of the serialization.  I.e., unless you're doing abnormal 
>tests as I did, you won't notice the difference.
>

From the PoOps (excerpted):
  The storage-operand update reference for the follow- ing
  instructions appears to be an interlocked-update reference as
  observed by other CPUs and channel programs.

• TEST AND SET
• COMPARE AND SWAP
(of course)

• AND (NI and NIY), when the interlocked-access facility 2 is installed
• OR (OI and OIY), when the interlocked-access facility 2 is installed
(at last!)

• ADD IMMEDIATE (ASI and AGSI), when the interlocked-access facility
  1 is installed and the first operand is aligned on an integral
  boundary corresponding to its size

The feature-dependent instructions are treacherous.  Programmers must
avoid them in multi-tasking code intended to be portable.

I consider it bad hardware design to introduce feature-dependent
instructions.  They should have remained invalid operations on models
lacking the interlock facility.

I believe NI and OI are primeval: they antedate multiprocessors and
became unsafe only at the advent of multiprocessors.

-- 
gil

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Re: CS/CDS instruction

2023-03-11 Thread Leonard D Woren
If some particular instruction set feature is installed, the 
definition of ASI/AGSI is enhanced to serialize the update, making it 
a simpler solution than a CDS loop or PLO.


In some performance testing a while back on a z14 or z15 which I think 
had the above serialization feature, the execution times for a very 
large number of executions of L / AHI / ST were very close to the same 
count of ASI.  If I recall, the ASI was a few percent slower, I guess 
because of the serialization.  I.e., unless you're doing abnormal 
tests as I did, you won't notice the difference.


/Leonard


Seymour J Metz wrote on 3/1/2023 1:33 PM:

In addition to the obvious instructions Phil mentioned, there is also PLO. I 
don't have any relevant performance data.


--
Shmuel (Seymour J.) Metz
http://mason.gmu.edu/~smetz3


From: IBM Mainframe Discussion List [IBM-MAIN@LISTSERV.UA.EDU] on behalf of 
Ituriel do Neto [03427ec2837d-dmarc-requ...@listserv.ua.edu]
Sent: Wednesday, March 1, 2023 3:52 PM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: CS/CDS instruction

Hi all,

Is there a similar instruction to CS or CDS, but using 64 bits register ?

I have a double word that contains a counter and using 64 bits instructions
would be faster to increment this value than manipulate it with other storage
areas and an even-odd pair of 32 bits registers.

Thanks in advance


Best Regards

Ituriel do Nascimento Neto
z/OS System Programmer

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Re: CS/CDS instruction

2023-03-10 Thread Mike Schwab
https://www.ibm.com/common/ssi/ShowDoc.wss?docURL=/common/ssi/rep_ca/1/897/ENUS122-001/index.html

IBM z16tm puts innovation to work while unlocking the potential of
your hybrid cloud transformation

IBM United States Hardware Announcement 122-001
April 5, 2022

Removal of support of the transactional execution and constrained
transactional execution facility: In a future IBM Z hardware system
family, the transactional execution and constrained transactional
execution facility will no longer be supported. Users of the facility
on current servers should always check the facility indications before
use.

On Fri, Mar 10, 2023 at 7:17 AM Peter Relson  wrote:
>
> The statement of direction is clear.
> That stated direction is to remove the transactional execution facility.
> I think that no information is yet available about "when" or whether it might 
> be done in stages.
>
> Paul G wrote
> >Transactional execution : software :: speculative execution : firmware.
>
> I'm not sure what that means. The transactional execution facility we are 
> talking about is a machine facility.
> Exploitation of that facility is under direct control of the software.
>
> Peter Relson
> z/OS Core Technology Design
>
>
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Where do Forest Rangers go to get away from it all?

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Re: CS/CDS instruction

2023-03-10 Thread Tom Marchant
On Thu, 9 Mar 2023 20:06:10 -0600, Paul Gilmartin  wrote:

>On Thu, 9 Mar 2023 18:17:14 -0600, Tom Marchant wrote:
>
>>IBM has announced that Transactional execution will be removed.
>>
>Entirely?  I read much earlier that it  was being removed partially.

From the z16 announcement 


Removal of support of the transactional execution and constrained transactional 
execution facility: In a future IBM Z hardware system family, the transactional 
execution and constrained transactional execution facility will no longer be 
supported. Users of the facility on current servers should always check the 
facility indications before use.


https://www.ibm.com/common/ssi/ShowDoc.wss?docURL=/common/ssi/rep_ca/1/897/ENUS122-001/index.html

-- 
Tom Marchant

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Re: CS/CDS instruction

2023-03-10 Thread Peter Relson
The statement of direction is clear.
That stated direction is to remove the transactional execution facility.
I think that no information is yet available about "when" or whether it might 
be done in stages.

Paul G wrote
>Transactional execution : software :: speculative execution : firmware.

I'm not sure what that means. The transactional execution facility we are 
talking about is a machine facility.
Exploitation of that facility is under direct control of the software.

Peter Relson
z/OS Core Technology Design


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Re: CS/CDS instruction

2023-03-09 Thread Ed Jaffe

On 3/9/2023 6:06 PM, Paul Gilmartin wrote:

On Thu, 9 Mar 2023 18:17:14 -0600, Tom Marchant wrote:


IBM has announced that Transactional execution will be removed.


Entirely?  I read much earlier that it  was being removed partially.


Partial disablement of anything is often a prelude to eventual permanent 
disablement...



--
Phoenix Software International
Edward E. Jaffe
831 Parkview Drive North
El Segundo, CA 90245
https://www.phoenixsoftware.com/



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Re: CS/CDS instruction

2023-03-09 Thread Paul Gilmartin
On Thu, 9 Mar 2023 18:17:14 -0600, Tom Marchant wrote:

>IBM has announced that Transactional execution will be removed.
>
Entirely?  I read much earlier that it  was being removed partially.

Transactional execution : software :: speculative execution : firmware.

But in the latter case, the designer has more control over its use.


>On Fri, 10 Mar 2023 10:51:59 +1100, Attila Fogarasi wrote:
>
>>The modern way is Transactional Execution.  PLO was developed decades ago
>>and works well by itself but doesn't co-exist well with CS/CDS.  

-- 
gil

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Re: CS/CDS instruction

2023-03-09 Thread Tony Harminc
On Thu, 9 Mar 2023 at 18:52, Attila Fogarasi  wrote:

> The modern way is Transactional Execution.


It would be if IBM hadn't announced that it's being discontinued.


> PLO was developed decades ago
> and works well by itself but doesn't co-exist well with CS/CDS.  From a
> performance perspective transactional execution is the way to go (TBEGIN
> instruction, etc. but you need to check CVTTX for availability of the
> facility).
>

And some time soon it will always not be available.

Tony H.

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Re: CS/CDS instruction

2023-03-09 Thread Tom Marchant
IBM has announced that Transactional execution will be removed.

-- 
Tom Marchant

On Fri, 10 Mar 2023 10:51:59 +1100, Attila Fogarasi  wrote:

>The modern way is Transactional Execution.  PLO was developed decades ago
>and works well by itself but doesn't co-exist well with CS/CDS.  From a
>performance perspective transactional execution is the way to go (TBEGIN
>instruction, etc. but you need to check CVTTX for availability of the
>facility).

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Re: CS/CDS instruction

2023-03-09 Thread Attila Fogarasi
The modern way is Transactional Execution.  PLO was developed decades ago
and works well by itself but doesn't co-exist well with CS/CDS.  From a
performance perspective transactional execution is the way to go (TBEGIN
instruction, etc. but you need to check CVTTX for availability of the
facility).

On Fri, Mar 3, 2023 at 4:38 AM Ituriel do Neto <
03427ec2837d-dmarc-requ...@listserv.ua.edu> wrote:

> Guys,
>
> Thank you, that's exactly what I need.
> I don't know how I didn't see it in Pop
>
>
> Best Regards
>
> Ituriel do Nascimento Neto
> z/OS System Programmer
>
>
>
>
>
>
> Em quarta-feira, 1 de março de 2023 às 18:34:12 BRT, Seymour J Metz <
> sme...@gmu.edu> escreveu:
>
>
>
>
>
> In addition to the obvious instructions Phil mentioned, there is also PLO.
> I don't have any relevant performance data.
>
>
> --
> Shmuel (Seymour J.) Metz
> http://mason.gmu.edu/~smetz3
>
> 
> From: IBM Mainframe Discussion List [IBM-MAIN@LISTSERV.UA.EDU] on behalf
> of Ituriel do Neto [03427ec2837d-dmarc-requ...@listserv.ua.edu]
> Sent: Wednesday, March 1, 2023 3:52 PM
> To: IBM-MAIN@LISTSERV.UA.EDU
> Subject: CS/CDS instruction
>
> Hi all,
>
> Is there a similar instruction to CS or CDS, but using 64 bits register ?
>
> I have a double word that contains a counter and using 64 bits instructions
> would be faster to increment this value than manipulate it with other
> storage
> areas and an even-odd pair of 32 bits registers.
>
> Thanks in advance
>
>
> Best Regards
>
> Ituriel do Nascimento Neto
> z/OS System Programmer
>
> --
> For IBM-MAIN subscribe / signoff / archive access instructions,
> send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
>
> --
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> --
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>

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Re: CS/CDS instruction

2023-03-02 Thread Ituriel do Neto
Guys,

Thank you, that's exactly what I need. 
I don't know how I didn't see it in Pop


Best Regards

Ituriel do Nascimento Neto
z/OS System Programmer






Em quarta-feira, 1 de março de 2023 às 18:34:12 BRT, Seymour J Metz 
 escreveu: 





In addition to the obvious instructions Phil mentioned, there is also PLO. I 
don't have any relevant performance data.


--
Shmuel (Seymour J.) Metz
http://mason.gmu.edu/~smetz3


From: IBM Mainframe Discussion List [IBM-MAIN@LISTSERV.UA.EDU] on behalf of 
Ituriel do Neto [03427ec2837d-dmarc-requ...@listserv.ua.edu]
Sent: Wednesday, March 1, 2023 3:52 PM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: CS/CDS instruction

Hi all,

Is there a similar instruction to CS or CDS, but using 64 bits register ?

I have a double word that contains a counter and using 64 bits instructions
would be faster to increment this value than manipulate it with other storage
areas and an even-odd pair of 32 bits registers.

Thanks in advance


Best Regards

Ituriel do Nascimento Neto
z/OS System Programmer

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Re: CS/CDS instruction

2023-03-01 Thread Seymour J Metz
In addition to the obvious instructions Phil mentioned, there is also PLO. I 
don't have any relevant performance data.


--
Shmuel (Seymour J.) Metz
http://mason.gmu.edu/~smetz3


From: IBM Mainframe Discussion List [IBM-MAIN@LISTSERV.UA.EDU] on behalf of 
Ituriel do Neto [03427ec2837d-dmarc-requ...@listserv.ua.edu]
Sent: Wednesday, March 1, 2023 3:52 PM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: CS/CDS instruction

Hi all,

Is there a similar instruction to CS or CDS, but using 64 bits register ?

I have a double word that contains a counter and using 64 bits instructions
would be faster to increment this value than manipulate it with other storage
areas and an even-odd pair of 32 bits registers.

Thanks in advance


Best Regards

Ituriel do Nascimento Neto
z/OS System Programmer

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send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN

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Re: CS/CDS instruction

2023-03-01 Thread Phil Smith III
Ituriel do Neto asked:
>Is there a similar instruction to CS or CDS, but using 64 bits register ?

 

CSG/CDSG. Look at Principles of Operation.


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Re: CS/CDS instruction

2023-03-01 Thread Tom Harper
CSG and CDSG in Pop. 

Sent from my iPhone

> On Mar 1, 2023, at 3:53 PM, Ituriel do Neto 
> <03427ec2837d-dmarc-requ...@listserv.ua.edu> wrote:
> 
> Hi all,
> 
> Is there a similar instruction to CS or CDS, but using 64 bits register ?
> 
> I have a double word that contains a counter and using 64 bits instructions
> would be faster to increment this value than manipulate it with other storage
> areas and an even-odd pair of 32 bits registers.
> 
> Thanks in advance
> 
> 
> Best Regards
> 
> Ituriel do Nascimento Neto
> z/OS System Programmer
> 
> --
> For IBM-MAIN subscribe / signoff / archive access instructions,
> send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN



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CS/CDS instruction

2023-03-01 Thread Ituriel do Neto
Hi all,

Is there a similar instruction to CS or CDS, but using 64 bits register ?

I have a double word that contains a counter and using 64 bits instructions
would be faster to increment this value than manipulate it with other storage
areas and an even-odd pair of 32 bits registers.

Thanks in advance


Best Regards

Ituriel do Nascimento Neto
z/OS System Programmer

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